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raja1
Explorer
Explorer
3,504 Views
Registered: ‎09-04-2015

IBERT test at PRBS-31-bit vs PRBS-15-bit pattern

Hi,

 

We are using XCVU3P device and running IBERT test at 28.05Gbps at GTY Quad 126. We see that on one of the lanes (MGT_X0Y8) is getting error in every 2-3 minute when PRBS-31-bit pattern is selected in Vivado, however, there are no errors observed with PRBS-15-bit pattern. What could be the reasoning behind the same? Can you please suggest us any steps for debugging the same?

 

Please note that we have built 4 such boards and we see this observation in only 1 board, the other 3 works fine at PRBS-31-bit pattern.

 

Regards,

Raja

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jheslip
Xilinx Employee
Xilinx Employee
3,425 Views
Registered: ‎06-30-2010

the PRBS 15 pattern would be stressing the link less than the PRBS31 p[attern. The fact that it only fails on one board out of 4 suggests something marginal, have you looking at the power supplies when the PRBS31 is running to check they are all in spec?
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venkata
Moderator
Moderator
3,243 Views
Registered: ‎02-16-2010

In addition to power supplies, please check the reference clock phase noise meets the requirement mentioned in the device data sheet. Please check Table 47 of DS923 for this details.
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