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Adventurer
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Registered: ‎11-20-2018

IDATAIN vs DATAIN in IDELAYE3 input port [xapp1315]

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Hi.

I'm using ultrasclae+ . I want to use the xapp1315  in my design for 1:7 deserialization.

In Xapp1315 design file, an external clock is used to enter the fpga through IBUFGDS.

image.png

But in my design, there are many other logics, so xapp1315 design can not be top file.

The main problem is that I have only 50MHz external input clock port, but this xapp 1315 design doesn't support this frequency.

The solution I thought was as follows.

image.png

Since the input of IDELAYE3 was no longer coming from the IO buffer, I used a DATAIN port instead of the IDATAIN port.

(I also changed the delay_src from IDATAIN to DATAIN).

 

However , the simulation results are different from the original xapp1315 design.

The rx_ready signal is not asserted. The output seems as if it continues to bitslip.

Is the way I thought it was wrong?

Is it a problem to create a differential clock in mmcm or is it a problem or is IDELAYE3 misused?

 

Thank you for reading me the long question.

 

Below code is part of XAPP1315.

 

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Moderator
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Registered: ‎08-08-2017

Re: IDATAIN vs DATAIN in IDELAYE3 input port [xapp1315]

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Hi @kangsungsik 

Okay , As you know the the necessary clocks in the design are derived as follows

The receiver source clock is multiplied by either 7 or 14 in an MMCM or PLL to meet the VCO frequency range, and then divided by two to generate the 1/2 rate sampling clock (rx_clkdiv2)
and by seven to generate the fabric pixel clock (px_clk). The 1/8 rate deserialized data clock (rx_clkdiv8) is generated from the 1/2 rate sampling clock MMCM or PLL output using a
BUFGCE_DIV to minimize clock skew between ISERDESE3 CLK and CLKDIV inputs.

This is valid if you are receiving frame clock which is 1/7 *  data rate .

Here you need to make some changes in the MMCM (M , D and 0)  setting as your clock is only 50 MHz.

Again as warning , we dont supoort the edits in application note and i dont know if Callibration State machine will work correctly in this case or not. This changes are at your own risk.

 

 

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Registered: ‎08-08-2017

Re: IDATAIN vs DATAIN in IDELAYE3 input port [xapp1315]

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Hi @kangsungsik 

In Summary section of this application note cleary mention the data rate limitations

Rreception and transmission of 7:1 data using low-voltage differential signaling (LVDS) for data transmission speeds of 415 Mb/s up to 1,100 Mb/s per line in HP I/Os and 1000 Mb/s in HR I/OS.

So the minimim supported clock is 415/7 MHz = 59.28 MHz

Additionally it is Source Synchronous 7:1 Serialization and Deserialization Using Clock Multiplication and targetted for certain applications (e.g VIDEO)

so if your data rate is 700 MHZ , i am not sure why you are receiving 50 MHz clock , you should get the 100MHZ clock syncronous with data.

Are you using 50 MHz system clock ?

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Adventurer
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Registered: ‎11-20-2018

Re: IDATAIN vs DATAIN in IDELAYE3 input port [xapp1315]

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Hi. @pthakare 

 

The data rate is 700MHz and my system clock is 100MHz.

I want to use this application to receive ADC data. 

And this ADC has only 50MHz ( 1/2 x its frame clock).

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Moderator
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Registered: ‎08-08-2017

Re: IDATAIN vs DATAIN in IDELAYE3 input port [xapp1315]

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Hi @kangsungsik 

Okay , As you know the the necessary clocks in the design are derived as follows

The receiver source clock is multiplied by either 7 or 14 in an MMCM or PLL to meet the VCO frequency range, and then divided by two to generate the 1/2 rate sampling clock (rx_clkdiv2)
and by seven to generate the fabric pixel clock (px_clk). The 1/8 rate deserialized data clock (rx_clkdiv8) is generated from the 1/2 rate sampling clock MMCM or PLL output using a
BUFGCE_DIV to minimize clock skew between ISERDESE3 CLK and CLKDIV inputs.

This is valid if you are receiving frame clock which is 1/7 *  data rate .

Here you need to make some changes in the MMCM (M , D and 0)  setting as your clock is only 50 MHz.

Again as warning , we dont supoort the edits in application note and i dont know if Callibration State machine will work correctly in this case or not. This changes are at your own risk.

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post