IO Assignment for PCIe Interface

[jimmy.thompson]

Morning,

How does Vivado decide where to place PCIe IO ports when using a IP core?  I am using a PCIe Gen3 AXI Bridge IP in a Virtex Ultrascale part.  When I go to assign my IO ports Vivado auto places my PCIe lanes, PCIe clock, and PCIe reset.  I believe that this is set by the .xdc file generated with my IP source however I do not know how to edit these features.

For example, it places my PCIe reference clock on MGTREFCLK1 but I want to change it to MGTREFCLK0.  Also, it auto places the PCIe reset on the PERSTN0 pin and I want to change the placement to a different IO.

Is it possible to edit these auto placed sites?  If so, how do I go about doing so?

Let me know if you need more info.

Thanks,

Jimmy

[austin]

j,

Typically, blocks like PCIe and MIG follow the exact placement as used on our demo boards.  Deviating from this placement means you may need to debug issues (as we did it one way, not all possible ways).

So, I would recommend staying as close to the known working examples as possible.  Are you able to make small changes safely?  If the core allows it, I would say yes.  What I would be careful of is assigning all the pins too early, forcing the design to try to use a non-optimal placement.  Generally, the best results use the fewest constraints initially.  Once the design fits and meets timing, the pins may be nailed down (fixed) where they like to reside.  The PCIe may have placement specific to certain tiles and pins (like a GT quad).  You may have no choices in the matter regarding the GT reference clock and TX/RX pins...

[jimmy.thompson]

Austin,

Thanks for the reply and info.

I'm using a custom carrier board so I'm unable to tweak the physical connections of the pins.  What I'm getting at is how do I overwrite the default placements that the core sets?  I need to move the reference clock to a different GT reference clock within the same quad and the PCIe reset to a different IO pin; I believe both of these changes are allowed.

When I try to reassign the pin, it says that the pins are already assigned in a read-only constraint file (I assume this is core generated).

Jimmy

[austin]

j,

You then need to modify the core source code.

That is a different (maybe non-existent) agreement (license).  Contact your Xilinx distributor to discuss.

[vsrunga · Accepted solution]

@jimmy.thompson

PCIE TX/RX locations are based on GT quad selected in the PCIE GUI. If you do not want to go with defaults, you can enable GT selection mode (using the Enable GT Quad Selection Advanced mode option) and choose the required quad

However make sure that you respect the recommended GT locations for the IP core given in appendix-B section of PG156.

To change the refernce clock you need to find the IBUFDS_GTE3 in the floor plan of the implemented design and privide the constarint in your top level file.

If you can upload your core configuration file(.xci) we can view your IP/Quad settings and provide clues on how to change the location.

Hope this helps

-Vanitha

[mkiernicki]

When you say "make sure that you respect the recommended GT locations" does that include the particular lanes? For example for a 4 lane, the rx ports[0-3] are mapped to F2,H2,K2 and M2. I would like to remap those to H2, K2, M2  and F2.