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Registered: ‎05-08-2018

IP clk_wiz:5.4 : what is the locked output port timing?

I am using the Xilinx IP clk_wiz:5.4.

I have two output clocks what a 3/4 phase_relation (ck1 , ck2).

I need to synchronize a signal crossing from the ck1 to the ck2, so I need for that to know in  which cycle are both clks starting the rising_edge together.

I am trying to use the locked output port but what I read in the doc is not the same as I am getting in simulation.

The documentation says the clocks will be available after 8 clk_in cycles from the locked is produced.

In the simulation, the clocks are produced 6 clk_in cycles after the locked...

I need to be sure of the locked timing for getting the correct cycke where both output clocks are having the rising_edge together..

Is the documentation right? ( PG065, Page 37

Safe Clock Startup feature enables stable and
valid clock at the output using BUFGCE after
Locked is sampled High for 8 input clocks


Why am I not getting the same in simulation?

Thanks in advance for any help!

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1 Reply
Registered: ‎02-09-2017

Hi @cgrandal,


Just to verify, have you enabled the Safe Clock Startup feature? It does not come with the MMCM by default, you have to select it when configuring the Clocking Wizard IP.


When that is enabled, it will insert a 8-bit register on the output of the Clock, effectively causing it to only be available to the rest of the logic after the Locked pin goes up + 8 clock cycles.



Andre Guerrero

Product Applications Engineer

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