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Observer gaurav_ag
Observer
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Registered: ‎11-13-2017

Initial state of RAMs after FPGA configuration

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Hi 

 

What is the init state of RAMs after FPGA configuration? 

 

Is it guaranteed to be zero always? 

 

Please let me know it more specifics are required to answer this question

 

Thanks

Gaurav

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Scholar dpaul24
Scholar
1,257 Views
Registered: ‎08-07-2014

Re: Initial state of RAMs after FPGA configuration

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@gaurav_ag,

Do you know the verilog / system verilog equivalent of the VHDL code you used above?

 

Its is very basic, just initialing a 2-D array.

You can use a loop and assign them to 0s.

 

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Scholar dpaul24
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Registered: ‎08-07-2014

Re: Initial state of RAMs after FPGA configuration

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@gaurav_ag,

 

In my TDP async RAM VHDL code, I do something like this:

 

type ramType is array (0 to maxSIZE-1) of std_logic_vector(minWIDTH-1 downto 0);

.

.

signal my_ram  : ramType := (others => (others => '0'));

 

to ensure my RAM contents are 0s.

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Observer gaurav_ag
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Registered: ‎11-13-2017

Re: Initial state of RAMs after FPGA configuration

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Thanks for the reply ..

does this ensure that the contents are 0s at the time of reconfiguration (that is programming of the FPGA).

Thanks
Gaurav
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Scholar dpaul24
Scholar
1,568 Views
Registered: ‎08-07-2014

Re: Initial state of RAMs after FPGA configuration

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@gaurav_ag,

 

You Q is already answered by this line: ....to ensure my RAM contents are 0s.

 

Yes it is guaranteed that they are 0s.

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Instructor
Instructor
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Registered: ‎08-14-2007

Re: Initial state of RAMs after FPGA configuration

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The bitstream generation defaults to loading zero into any RAM bit or flip-flop that isn't otherwise initialized by your code.  Initializing the RAM to all zero as in dpaul's code ensures that your simulation sees the same behavior as the actual device on startup.

-- Gabor
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Scholar markcurry
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Registered: ‎09-16-2009

Re: Initial state of RAMs after FPGA configuration

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I believe the new UltraRAMs are different, so those won't necessarily follow this rule?

 

UltraRAMS can't be loaded via INIT.  UG573 indicates:

 

The UltraRAM memory is initialized to all 0's during power up or device reset. There is
no user defined INIT attribute and therefore the content of the SRAM array cannot be
initialized to user defined values.

 

I read this as a power up will init UltraRAMs to all zeros, but not necessarily a reconfiguration?  I'm not clear on what a "device reset" is - that term's not defined. Is it a GSR?  If so, then a reconfiguration would re-init UltraRAMS to all zeros.

 

Regards,

 

Mark

 

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Observer gaurav_ag
Observer
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Registered: ‎11-13-2017

Re: Initial state of RAMs after FPGA configuration

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citing another INIT attribute related discussion which also suggests that values in RAM may not always be 0.

 

https://www.xilinx.com/support/answers/4328.html

 

... this discussion says that the PAR tool may change the INIT attribute, which in turn can change the values of RAM after re-configuration.

 

Thanks

Gaurav

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Registered: ‎01-08-2012

Re: Initial state of RAMs after FPGA configuration

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Let's not forget AR#21870, which says that the Block RAM values can change even if WE is low.

 

I found this (to my chagrin) in Virtex-2P, when simply clocking a Block RAM from a DCM could be enough to corrupt the RAM/ROM content if the CE of the RAM was active at the same time that the DCM decided to generate a glitch on its clock output.

 

EDIT: I was very happy when Xilinx:

  1. decided to drop the DCM in favour of the (less glitchy) MMCM, and
  2. made the Block RAMs slightly wider so that there was an extra bit available for parity checking, and
  3. published AR#21870, which explained what was going on and what to do about it.
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Observer gaurav_ag
Observer
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Registered: ‎11-13-2017

Re: Initial state of RAMs after FPGA configuration

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@gszakacs

 

Hi Gabor 

 

Can you please address the questions regarding INIT above? 

 

Thanks

Gaurav

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Scholar dpaul24
Scholar
1,354 Views
Registered: ‎08-07-2014

Re: Initial state of RAMs after FPGA configuration

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@gaurav_ag,

 

citing another INIT attribute related discussion which also suggests that values in RAM may not always be 0.

https://www.xilinx.com/support/answers/4328.html

 

... this discussion says that the PAR tool may change the INIT attribute, which in turn can change the values of RAM after re-configuration.

 

Did you see the AR# date? It is : 04/24/2007 ..... more than 10 years ago!

And also it is talking about PAR, a feature of the ISE (not Vivado). This applies to older Xilinx devices, series6 and below.

 

So now the question is, are you using series7 devices or something older? Are you using ISE?

If yes then you might have a reason to worry, else not (you can use the method of RAM init as I have already explained).

 

 

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Observer gaurav_ag
Observer
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Registered: ‎11-13-2017

Re: Initial state of RAMs after FPGA configuration

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@dpaul24

 

Ok ... understood the point. 

 

Do you know the verilog / system verilog equivalent of the VHDL code you used above?

 

Thanks

Gaurav

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Scholar dpaul24
Scholar
1,258 Views
Registered: ‎08-07-2014

Re: Initial state of RAMs after FPGA configuration

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@gaurav_ag,

Do you know the verilog / system verilog equivalent of the VHDL code you used above?

 

Its is very basic, just initialing a 2-D array.

You can use a loop and assign them to 0s.

 

--------------------------------------------------------------------------------------------------------
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All PMs will be ignored
--------------------------------------------------------------------------------------------------------

View solution in original post

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Observer gaurav_ag
Observer
1,028 Views
Registered: ‎11-13-2017

Re: Initial state of RAMs after FPGA configuration

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Sorry .. should have clarified .. 

 

I am instantiating an xpm memory manually, and I want to initialize that.

 

Thanks

Gaurav

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