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Contributor
Contributor
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Registered: ‎07-03-2018

Internal "clock" divider latency

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Hi everyone,

 

When I create 2 signals with 10ms period from clock 62.5MHz and 122.88MHz, I saw that the distance between 2 signals is not constant after running a long time. Anyone can explain this issue? I thought that it will remain the distance between 2 signals because it has the same period (10ms)?

Ps: With clock 62.5MHz, I have 625000/2 cycles for high level '1' and 625000/2 cycles for low level '0' 

      With clock 122.88MHz, I have 1228800/2 cycles for high level '1' and 1228800/2 cycles for low level '0' 

 

Thank you,

Yurivn

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Explorer
Explorer
342 Views
Registered: ‎06-25-2014

Re: Internal "clock" divider latency

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How are your 2 clocks generated? If they are from 2 crystals, then you are seeing the ppm differences between them. If using an MMCM then you will probably see the actual frequency is not the same as the requested. 

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Moderator
Moderator
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Registered: ‎08-08-2017

Re: Internal "clock" divider latency

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Hi @yurivn 

Can you elaborate more on distance between two signals ?  May be you can attach the Simulation or ILA screenshot explaning the same.

If i presume correctly you mean the phase difference between two signals is not constant throughout , Is it the case?

Did your observations based on Simulation or Hardware results ?

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Internal "clock" divider latency

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Did you mean the two frequencies to be integer divisions of each other ?

 Thinking of the findamental sine wave you have, 122.88, and 62.5 , they are not integer divisions of each other,

If they were 122.88 and 61.44, as used in telecom , then they would stay in sync,

Two different frequencies not integer division related are goign to beet, as you have seen.

 

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Highlighted
Explorer
Explorer
343 Views
Registered: ‎06-25-2014

Re: Internal "clock" divider latency

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How are your 2 clocks generated? If they are from 2 crystals, then you are seeing the ppm differences between them. If using an MMCM then you will probably see the actual frequency is not the same as the requested. 

View solution in original post

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Contributor
Contributor
252 Views
Registered: ‎07-03-2018

Re: Internal "clock" divider latency

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@andrewlan @drjohnsmith @pthakare 

 

A problem is 2 clocks are generated from 2 different clock source, so it makes a different between 2 clocks after a long time running.

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