Issues with High Speed SelectIO Wizard in Async mode
I am running into intermittent issues with a High Speed SelectIO Wizard generated module. Initially the module was working as expected, but I started running into times where the module would not come out of reset successfully. This would happen after recompiling my design for simulation after making an unrelated change. I've narrowed this down to the Wizard Reset Controller being stuck in the WAIT_FOR BSC_DLY_RDY state. It looks like all of the dly_rdy signals from the BS Controllers are never transitioning to 1.
Here is the snippet of code in the reset controller that the state machine is stuck in (note, for some reason designer has commented out timing out of this state and it hangs here forever):
timeout_cntr_rst <= `pTCQ 1'b1;
hssio_state <= `pTCQ ASSERT_BSC_EN_VTC;
//else if (wait_bsc_dly_rdy_timeout)
// hssio_state <= `pTCQ ASSERT_ALL_RESETS;
hssio_state <= `pTCQ WAIT_FOR_BSC_DLY_RDY;
Unfortunately, the BSC controller is a primitive and I am not able to debug further into why all 8 BSCs do not drive DLY_RDY active after reset.
Details of my design are:
Vivado 2016.4, VCS-MX 2016-06-1
HIgh Spped IO WIzard core:
Data Rate: 1250-Mb/s
PLL Input clock: 250-Mhz
RX DLY and TX DLY: VAR-LOAD COUNT
ISERDES/OSERDES : x4 (312.5-Mhz rxclk/txclk)
All nibbles are used. 3 TX, 7 RX differential pairs. No clock pins (PLL clock comes from fabric)
I am driving rx_en_vtc[i], tx_en_vtc[i], and en_vtc_bsc[i] all to 0, as I am handling delay setting in my own logic. Everything else looks good..PLLs all lock, PLL output clocks are correct, I believe I am driving rst into core properly, etc. Also, this is very intermittent...some builds work and some hang in this state.