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Observer
Observer
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Registered: ‎07-14-2015

KCU105: Recovered Clock of GTHE3

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I am migrating an existing Kintex-7 design to a new Kintex Ultrascale design.  I am using the KCU105 board to do firmware prototyping for the migration.  However, I am running into a very strange recovered clock jitter issues on the KCU105.  In my old design (see OldKintex7Design.JPG attachment) the GTX recovered clock has a very clean spectral and very low jitter (~25 ps RMS jitter).  In my new design (see Kcu105Design.JPG attachment) and using the same fiber link, I am getting a weird sideband frequency modulation around the CDR recovered clock's fundamental frequency of 119 MHz.  This frequency modulation is making my clock not very low jitter (few hundred ps RMS jitter).


I have attached an achieved Vivado 2016.4 project for my KC105 build to this Xilinx web forum (see Kcu105GthCdrRecClkTest.tar.gz attachment). Is there a special RX CDR configuration that I am missing in my Xilinx IP core wizard?  If yes, how do I set it? 

Kcu105HardwareSetup.jpg
OldKintex7Design.JPG
Kcu105Design.JPG
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Observer
Observer
7,104 Views
Registered: ‎07-14-2015

At the end, we gave up on trying to tune the GTH CDR and added an external clock jitter cleaner IC to clean up the CDR clock to solve this issue.

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Moderator
Moderator
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Registered: ‎02-16-2010
How are you bringing the RECCLK to the board pin? With UltraScale, you can use OBUFDS_GTE4 primitive to get the RECCLK signal outside FPGA.
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Observer
Observer
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Registered: ‎07-14-2015

See Kcu105GthCdrRecClkTest.vhd attachment.

 

>> How are you bringing the RECCLK to the board pin?

 

On the KCU105 development board, we are bring in the 238 MHz reference clock on the GT CLK SMA interface (pin V6/V5). We are driving the recovered 119 MHz clock on the GPIO SMA interface (pin D23/C23).

 

>> With UltraScale, you can use OBUFDS_GTE4 primitive to get the RECCLK signal outside FPGA.

 

Ok, but we have a requirement to drive the recovered clock on a standard OBUFDS.  Plus, I doubt the FM modulation of the recovered clock will go away with using the recovered clock on a GT CLK pin.

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Anonymous
Not applicable
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We observe the same spurs with the recovered clock from the GTHE3 receivers.

 

For a 160MHz clock the spurs appear +/- 400kHz above and below the recovered clock. We have tried to evaluate where this comes from, but to the best of our knowledge there is no 400kHz clock in our logic, so we assumed that it is some CDR loop leaking in the signal.

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Observer
Observer
7,105 Views
Registered: ‎07-14-2015

At the end, we gave up on trying to tune the GTH CDR and added an external clock jitter cleaner IC to clean up the CDR clock to solve this issue.

View solution in original post

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