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trenz-al
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Registered: ‎11-09-2013

KCU105 VREF pins

it seems that KCU105 has VREF pins of ALL banks FLOATING in the air, that includes DDR4 banks, FMC banks, just all VREF not connected to anything, no resistor, no cap no nothing.

 

is this correct for Kintex Ultrascale?

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austin
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Registered: ‎02-27-2008

t,

 

If not configured to use a Vref, it is not needed.

 

So, the question becomes, what do you do when you want to use a Vref IO standard (I don'y know)?

 

I find only two not connected, on sheet 7.  Every other one is connected (to something).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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trenz-al
Scholar
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Registered: ‎11-09-2013

KCU105

REV 1

Date 11/13/2014

 

sheet 4, banks 44,45 DDR4 - VREF open

sheet 5, bank 46 DDR4 - VREF open

sheet 6, banks 47,48 FMC - VREF open

sheet 7, banks 64,65 HR banks - VREF open

sheet 8, banks 66,67 FMC - VREF open

sheet 9, banks 68 FMC - VREF open

 

until today to my best knowledge

 

DNP

 

means: DO NOT POPULATE, those components are NOT INSTALLED and NOT PRESENT on the PCB

 

hence, ALL VREF pins are FLOATING !!

 

UG583 page 21:

 

When utilizing Internal VREF, tie the VREF pin to ground with a 500Ω resistor.

 

so I would assume, if VREF is not connected, and the 500 ohm is also missing, then those banks can not use external and can not use internal VREF.

 

so how come so? and DDR4 works..? Somewhere is a mistake but where?

 

now if ther DNP would DO populate, then VREF caps are still missing:

 

ug583 page 118:

In VREF supply stabilization, one capacitor per pin is placed as close as possible to the VREF
pin. The capacitors used are in the 0.022 μF – 0.47 μF range.

 

those caps are not at all in the KCU schematic, so if the DNP parts would be fitted the vref caps would still not be there..

 

UG571 page 19:

IMPORTANT: In banks where the input I/O standard has an input reference voltage requirement and
uses an internally generated VREF (INTERNAL_VREF or VREF scan), connect the dedicated VREF pin to
GND with a 500Ω or 1KΩ resistor.

 

the OPTION leave VREF floating is never mentioned, it also nowhere said how to connect VREF in the banks where VREF is not needed.

 

I would say 1K or 500R is needed as there are no other docuemtns, well except KCU105 schematic?

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austin
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Registered: ‎02-27-2008

That is odd,

 

Sheet 4 has it connected.

 

https://secure.xilinx.com/webreg/clickthrough.do?cid=379171&license=RefDesLicense&filename=kcu105-schematic-xtp392.zip&languageID=1

 

???

Austin Lesea
Principal Engineer
Xilinx San Jose
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trenz-al
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Registered: ‎11-09-2013

NO, in the schematic I downloaded last week it is DISCONNECTED.

Let me check this week, maybe it was changed over the weekend.

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trenz-al
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schematic download today from the link provided

 

sheet 4:

 

VREF_44_AD23 only connection to R684 with no value and marked DNP do not populate

VREF_45_AF19 only connection to R685 with no value and marked DNP do not populate

 

so both and all VREF pins present on page 4 are FLOATING

 

or am I mistaken?

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austin
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Registered: ‎02-27-2008

I'd have to look at the board...

 

Maybe its a schematic error (DNP)?  Or maybe you can choose and stuff them if needed?

Austin Lesea
Principal Engineer
Xilinx San Jose
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trenz-al
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Registered: ‎11-09-2013

well, I do not know.

 

it was possible done to support "assembly options" to select best, but well there seems to be no single valid source of information how to deal with VREF in Ultrascale, I know what the docs say, but it does not fully align with KCU105.

 

I am designing several Ultrascale products, and I would like to avoid any mistakes, and I do not have PCB place free to add "unused optional" DNP components for all banks.

 

Ok actually my primary issue question is: when using DDR4 should I

1 connect the KU VREF to DDR4 VREF?

2 connect R dividers to both, not not connect them together?

3 500R to GND for KU and VREF for DDR4

 

I have opted for 3

 

 

 

 

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austin
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Registered: ‎02-27-2008

t,

 

Look at the BOM:

 

https://secure.xilinx.com/webreg/clickthrough.do?cid=379173&license=RefDesLicense&filename=kcu105-bom-rdf0348.zip&languageID=1

 

Some are DNP.

Austin Lesea
Principal Engineer
Xilinx San Jose
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jonas_31
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Registered: ‎03-24-2016

In BOM alle resistors connected to DDR4 bank VREF pins are DNP.

I would like know how to do it right.
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austin
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Registered: ‎02-27-2008

j,

 

If the standard requires a Vref, then you need to supply it.  If not, then they may be left unused.

 

A signal integrity CAD tool is used to verify the IO design.  If the design did not use Vref IO standards, then they were not needed.

 

It could be (often is) the board is designed before the completed botstream is ready.  The designer may have initially specified (used) them, and later decided they did not need them.

 

So the question is:  do you require an IO standard with a Vref?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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jonas_31
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Registered: ‎03-24-2016

a,

 

I need exactly the same DDR4 memory topology and size like designed at kcu105.

The only question is, what is wrong or right.

 

In example for DDR4 DQ signals ultrascale use IOSTANDARD POD10_DCI and VREF (UG571 page 116..118).

PCB design user guide UG583 page 21 states, when utilizing Internal VREF, tie the VREF pin to ground with a 500Ω resistor.

 

Kcu105 is using DDR4 POD_DCI with unconnected VREF pins and it works.

 

It seems to be a discrepance in documentation and practice.

How can I make it right in new designs?

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austin
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j,

 

In ug571, the POD IO standard when used as an output requires no use of the Vref.

 

If the POD IO standard is used as an input, then it may require a Vref value to function properly. (example page 30).

 

 

Austin Lesea
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Xilinx San Jose
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jonas_31
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a,

 

sorry but this is not helpful.

 

I think, all users who want to know how to do it right, look at schematic of virtex ultrascale eval vcu108.

There VREF-Pins are connected like expected and described in user guides.

 

It keeps unclear if unconnected VREF-Pins like at kcu105 is a problem or not.

 

Best..

austin
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Registered: ‎02-27-2008

j,

 

I apologize if I am not helping.

 

If the design requires an IO standard which uses Vref, then they need to connect to a Vref (reference voltage).  If not, then those pins may be used as IO, or left unconnected.

 

The demo boards are built for a set of example designs.  If not required, the Vref on a bank may not be connected to a Vref.

Austin Lesea
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Xilinx San Jose
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vladmashari
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Registered: ‎04-03-2016

a,

 

So if Vref is not required, according to pg150, page 91: 

"The dedicated Vref pins in the banks used for DDR4 must be tied to ground with a resistor value specified in UG571 (Which is 500R or 1K as Jonas said)"

 

How come this is not implemented on the EVB?

Is this the right implementation, in case VREF is not required?

 

 

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austin
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v,

 

That is new.  I have no idea why that is there.  The Vref IO pins were (are?) identical to a regular IO pin as far as I know.

 

That they (now?) suggest a resistor is a puzzle to me as well.

 

It has been 6 years since I did IC design (and looked at the schematics of the devices).

 

I will go ask.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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austin
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Here is the answer:

 

"In Ultrascale, VREF is a dedicated pin, unlike 7-series and earlier families. We were somewhat late in the game, when it was ascertained that unused VREFs should be  gnd-ed. There are ESD and other concerns that drive this rule.

We decided that for the boards that have already been laid out, we will let them be, as the risk was pretty low. That is why KCU105 is the way it is."

 

Sorry for the delay.  I did not know the device had dedicated Vref pins that were not also IO pins.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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