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Adventurer
Adventurer
9,243 Views
Registered: ‎07-26-2013

KU GTH Tx buffer bypass, questions about restart and alignment

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Two questions:

 

1. I am interested in obtaining deterministic skew (not necessarily zero skew) for multiple GTH Tx outputs of a Kintex Ultrascale. I have done this with a closed-loop approach that uses the Tx PI, but am wondering if the tx buffer bypass will do what I want automatically.  The TX Buffer Bypass section of UG576 states that the TX phase alignment circuit can be used to minimize skew between GTH transceivers. Table 3-17 states that phase alignment achieves "lower and deterministic latency". However the alignment description refers to XCLK alignment which is still a parallel clock. My experiments indicate that when the FPGA starts up and runs the alignment procedure in bypass mode, the skew is indeed lower than when the buffer is enabled but is still random within a range of several UI. I suspect that even if the XCLKs are aligned, the serial outputs are not necessarily bit-aligned and therefore deterministic skew at the serial level is not possible. Is this true?

 

2. I am using a GTH example design for the KCU105 with Tx buffer bypassed. The example design includes transmitter buffer bypass controller logic as described in PG182. When the FPGA gets programmed, the phase alignment runs automatically and I see gtwiz_buffbypass_tx_done_out=1 amd gtwiz_buffbypass_tx_error_out=0 as expected. However if I reset all GTH Tx PLL and datapath then pulse gtwiz_buffbypass_tx_start_user_in I see gtwiz_buffbypass_tx_done_out go low but never go high. I tried manually asserting gtwiz_buffbypass_tx_reset_in before asserting start but it had no effect. Is there any special timing or sequence required for these signals when restarting phase alignment after Tx PLL/datapath reset?

 

Thanks,

Jason

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Moderator
Moderator
16,858 Views
Registered: ‎02-16-2010
Are you using multi-lane buffer bypass mode?

I find the following PG182.
By default, the reset helper block gtwiz_reset_tx_done_out output is wired to the transmitter buffer bypass controller helper block gtwiz_buffbypass_tx_resetdone_in input. A rising edge on this port automatically initiates the transmitter buffer bypass procedure.

So, tx pll/datapath reset should initiate buffer bypass procedure automatically.
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Moderator
Moderator
16,859 Views
Registered: ‎02-16-2010
Are you using multi-lane buffer bypass mode?

I find the following PG182.
By default, the reset helper block gtwiz_reset_tx_done_out output is wired to the transmitter buffer bypass controller helper block gtwiz_buffbypass_tx_resetdone_in input. A rising edge on this port automatically initiates the transmitter buffer bypass procedure.

So, tx pll/datapath reset should initiate buffer bypass procedure automatically.
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Adventurer
Adventurer
9,183 Views
Registered: ‎07-26-2013

Thank you for the reply. I received some feedback via email that if the Tx PI (phase interpolator) is still enabled then it will affect the serial alignment. I removed the Tx PI control signals in the GT wizard and rebuilt the design, and now the alignment is working as expected (as are the tx buffer bypass control/status signals). Not being able to use the Tx PI to fine-tune the skew after initial alignment is an issue, but we have a workaround on the board.

 

Thanks,

Jason

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Observer
Observer
5,804 Views
Registered: ‎09-22-2016

Hi,

 

I have a similar problem. I must have a deterministic relationship between 8 different lanes (GTH) after all the reset and power-up procedures. I was using TX Buffer Bypass, but without success. Do you have any good clue? With or without TX Buffer Bypass, with or without TX Phase Interpolator? Is there any good reference design?

 

Best regards,

Daniel Dinis

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Visitor
Visitor
3,233 Views
Registered: ‎10-13-2017

Hello, I want to obtain deterministic skew for multiple GTH Tx outputs of a Kintex Ultrascale when power on or reset. I have used the buffer bypass to realize it. But the PI can't work. I saw that you have done it by a closed-loop approach that uses the Tx PI. I wonder that how to do it. I would appreciate it for your help.

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Visitor
Visitor
3,228 Views
Registered: ‎10-13-2017

Hello, I have another querstion about PIPPM. I want to set PI to adjust the delay multi-lane GTH. I have done it using PI Code Stepping Mode. But the stride is small.  I want to set the PI code directly by assert the register TXPIPPMOVRDEN='1'. And then I set the TXPI_PPM_CFG through the DRP port. As guided in UG576,  three times.The most significant bit needs to be pulsed (asserted High and then Low) for the TX PI to register the new 7-bit value of TXPI_PPM_CFG[6:0]. So I set the TXPI_PPM_CFG three times and just change the most significant bit(0-1-0). However, I can't realize that  what I want to achieve. Thank you very much.

 






 


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Xilinx Employee
Xilinx Employee
3,152 Views
Registered: ‎06-01-2017

Hi optics_bobo,

 

Check the EN, PD, SEL, and OVRDEN ports/attributes, and try the sequence below:

 

1. Set TXPIPPMPD port to 0
2. Set TXPI_SYNFREQ_PPM[0] to 1
3. Set TXPIPPMEN port to 1
4. Set TXPIPPMOVRDEN port to 1
5. Set TXPIPPMSEL port to 1
6. Set TXPI_PPM_CFG[6:0] to the desired PI shift value (for eg decimal 32 = hex 20)
7. Set TXPI_PPM_CFG[7] to 1 while holding the TXPI_PPM_CFG[6:0] to the desired value in step 5 (hA0)
8. Set TXPI_PPM_CFG[7] back to 0 (h20)
9. Repeat steps 6 through 8 to change the PI shift to another desired value

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Visitor
Visitor
2,755 Views
Registered: ‎10-13-2017

Hello,

    It has no effect in phase alignment directly as the sequence that you guide. The evaluate board that I used is the KCU105. And the serial tansceivers I used is GTH. Is there any examples that using the phase alignement directly?

    I would appreciate it for your help.

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Visitor
Visitor
2,575 Views
Registered: ‎10-13-2017

Hi, Jason

    I am using multilane GTH in the KCU105 board. I must have a deterministic relationship between  different lanes (GTH) after all the reset and power-up procedures. As the datasheet of UG576, the method of TXBUF bypass can really solve my problem. However, the PI Controller can not be used to tune the delay after initial the phase alignment procedure. I want to have a desirable skews among the different lane. So I hope the PI Controller can function well after a initial alignment.

From the poster, I know that you have achieved the multi lane alignment with a close-loop mode by using the PI controller. Could you share me the idea or methods to me, and I would appreciate you for your help.

 

sincerely.

 With my best wished to you.

 

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