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markmiw
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Registered: ‎02-28-2019

Kintex Ultrascale+ Ibis Model Description

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I am trying to get some clarification on some of the models in kintexuplus.ibs

 

Particularly I wanted to know the difference between...

 

HP_LVDS

HP_SUB_LVDS

HP_LVDS_DT_I

HP_LVDS_DT_AC_COUPLED_I

HP_LVDS_PE1600

HP_LVDS_MAIN

HP_LVDS_PE

 

I am assuming HP_LVDS vs HP_LVDS_DT_I is that HP_LVDS_DT_I has an internal 100 ohm termination?

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gnarahar
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Registered: ‎07-23-2015

@markmiw  

HP_LVDS:  LVDS with no internal termination

HP_SUB_LVDS:  SUB_LVDS Buffer

HP_LVDS_DT_I:  LVDS Input with internal termination (DIFF_TERM)

HP_LVDS_DT_AC_COUPLED_I: LVDS input for AC coupled links

HP_LVDS_PE1600: LVDS with Pre-Emphasis 

HP_LVDS_MAIN & HP_LVDS_PE: Used in HP_LVDS_PE1600 under [Driver Schedule] 

Do take a look at Table 1-55 UG571 v1.10 Page#128 for attributes of LVDS IO standard that will help you understand the above.  

The recommended method to generate IBIS model is through Vivado so that it maps the corresponding IBIS model to your pinout based on your settings. Do take a look at this blog post I authored where I described the method to generate IBIS model from Vivado 

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/The-World-of-Hardware-Simulation/ba-p/936961

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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gnarahar
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Registered: ‎07-23-2015

@markmiw  

HP_LVDS:  LVDS with no internal termination

HP_SUB_LVDS:  SUB_LVDS Buffer

HP_LVDS_DT_I:  LVDS Input with internal termination (DIFF_TERM)

HP_LVDS_DT_AC_COUPLED_I: LVDS input for AC coupled links

HP_LVDS_PE1600: LVDS with Pre-Emphasis 

HP_LVDS_MAIN & HP_LVDS_PE: Used in HP_LVDS_PE1600 under [Driver Schedule] 

Do take a look at Table 1-55 UG571 v1.10 Page#128 for attributes of LVDS IO standard that will help you understand the above.  

The recommended method to generate IBIS model is through Vivado so that it maps the corresponding IBIS model to your pinout based on your settings. Do take a look at this blog post I authored where I described the method to generate IBIS model from Vivado 

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/The-World-of-Hardware-Simulation/ba-p/936961

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
------------------------------------------------------------------------------------------------------------------------

View solution in original post

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markmiw
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Registered: ‎02-28-2019

Thank you!

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