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Explorer
Explorer
2,666 Views
Registered: ‎07-10-2013

Kintex Ultrascale Transceiver RX Support For SSC

The datasheet (and other product information) for Kintex Ultrascale (KUS) devices cite support for transceiver RX spread-spectrum clocking (SSC).  The same is the case as well for Virtex Ultrascale (VUS), Kintex Ultrascale+ (KUS+) and Virtex Ultrascale+ (VUS+) devices.

 

Past products, such as Virtex-7 FPGAs for instance, also claimed to have general support for SSC, yet it appeared to be the case upon closer examination that SSC was in fact supported only for specific datarates and/or serial data coding schemes, which constraints were not hinted at in any product information.  For instance, an XC7VX330T-2FFG1157C, which would appear (per the DS183 datasheet) to be able to support standard SSC (33KHz modulation, 5000PPM max downspread) for any supported datarate including the 10Gbps datarate of interest for an application here, in fact cannot support 10Gbps SSC (per second-hand input from XIlinx support staff).

 

Where is information available for KUS (and VUS, KUS+ & VUS+) devices regarding which transceivers, data rates and coding schemes will in fact support use of SSC serial RX data; or alternatively, which transceivers, data rate ranges and types of coding schemes are known to not be able to work with SSC serial RX data?

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2 Replies
Xilinx Employee
Xilinx Employee
2,619 Views
Registered: ‎08-07-2007

Re: Kintex Ultrascale Transceiver RX Support For SSC

hi 

 

 

 

 

 

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Explorer
Explorer
2,607 Views
Registered: ‎07-10-2013

Re: Kintex Ultrascale Transceiver RX Support For SSC

Boris,

 

Thank you for your reply.

 

I see from the product information (DS890, Table 18) that while Ultrascale+ (US+) parts support PCIe Gen4, Ultrascale (US) parts are (only) capable of "operating at Gen4 data rates".  Please outline the differences between the US and US+ parts that prevent the former from supporting PCIe Gen4.

 

In an application here, a proprietary protocol needs to be supported that is virtually identical to PCIe Gen3 (8Gbps) and PCIe Gen4 (16Gbps), including use of SSC, with the only exception of operating at a datarate of 10Gbps.  For the application the FPGA xcvr need only perform SSC RX (no transmission, no PICe endpoint or root port, etc.).

 

Given US/US+ support for PCIe, please characterize how likely it should be to be able to implement the application requirements: no way (known issues prevent SSC RX at 10 Gbps); 50/50 (no known issues, but 10Gbps SSC RX may or may not be possible, cannot tell without characterization); almost certain success (no known issues, a piece of cake given existing similar PCIe SSC RX functionality at 16Gbps).

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