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drjohnsmith
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Registered: ‎07-09-2009

Kintex Ultrascale, Voltage on JTAG pins

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Kintex Ultra scale parts

 

Can run the JTAG pins at 1V8,

 

What is the Vout High and Low, and Vin High and Low thresholds,

 

can't seem to find the data 

 

any pointers please

 

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gnarahar
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@drjohnsmith 


 Yes you dd mention that the volts for the select IO pins "SHOULD" be the same as the JTAG  pins earlier, Thank you for that,

   I must be getting old as I try not to design to 'should' or best guess , unless I have to.

_____________________________________________________________________________________________________

 

My bad, could have worded it better. Realized it (use of word "should") after seeing this post & backtracked to the post I made.  


 As for using TCL and getting an IBIS model , and simulating that

   the other extreme, a bit of a hammer to crack a nut ,

    As an engineer, not the best use of my time for a 'simple' JTAG pin voltage VoH and VoL spec, 

 


Agree with IBIS simulation being an Overkill. It was just a suggestion in case you had to be spot on with Voh, Vol spec for the Tx/Rx device.  

 


 I was just expecting to be able to read a data sheet to find these numbers 

 

 


Agree. Will take this feedback and send it across. 

 


 La de Dah, As an engineer, I've designed the question out now,

   needed to move on,  I've added more chips to the design, which I know the data sheet for and I have used to drive the JTAG pins.  Had to explain why at design review, as it added extra cost, which although small per board, had to be justified, but there you go, 


Got it. Thanks for the background regarding this query.  
 



   

 

 

- Giri
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muzaffer
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@drjohnsmith what you're looking for should be in https://www.xilinx.com/support/documentation/data_sheets/ds892-kintex-ultrascale-data-sheet.pdf most probably table 9 or 10.

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drjohnsmith
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@muzaffer, I dont dis agree,

    the data 'should' be in the data sheet 

 

after all, the JTAG pins are part of the package, 

 

But I can't see the Voh and Vol max and min specs for the JTAG pins on the kintex ultra scale parts.

 

Anyone else seen them .. ? 

 

I can guess, but with a 1000 dollar plus part, rather not, 

   

 

Table 87 in the data sheet has timings, but no Voh / Vol or Vih /Vil.

 

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gnarahar
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@drjohnsmith JTAG pins operate on LVCMOS IO Standard of VCCO_0 voltage. So in your case, LVCMOS18 specs is what you should be looking at

 

Below snippet from Page#137 of UG570 

 

jtag_io_std.JPG

- Giri
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drjohnsmith
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Thank you

 

yep, saw that the interface volts depends upon a few things,

 

were running JTAG bank at 1v8

 

but I can't find the Voh and Vol , of the Vinh and Vinl specifications 

 

Are they the same as the select IO pins at 1V8 LVCMOS ?

   I doubt it as these JTAG pins will have ( I guess ) a  very different pin structure in the silicon to the multi capable Select Io pins.

 

 

 

   

 

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gnarahar
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 but I can't find the Voh and Vol , of the Vinh and Vinl specifications 

 Are they the same as the select IO pins at 1V8 LVCMOS ? 

 


Yes, the Vil,Vih,Vol,Voh specs of LVCMOS18 should be applicable for the JTAG pins too. 

 

I do not believe JTAG pins have a different set of Vil,Vih,Vol,Voh specifications since if they were, it would have been explicitly mentioned in the Datasheet. Irrespective of how their internal structure is, when they support LVCMOS18, they will adhere to the LVCMOS18 specifications (Vil,Vih,Vol,Voh) in datasheet. 

- Giri
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drjohnsmith
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'should'....

 

 

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austin
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The configuration users guide, and the datasheet state JTAG operates from Vccaux. Vccaux is 1.8v. At these technology nodes below 28nm, There are no 3.3v transistors in the nodes, so 3.3v IO requires cascading 1.8v devices. JTAG works just fine at 1.8v, so 3.3v JTAG is not a requirement (using LVCMOS 1.8v instead).
Austin Lesea
Principal Engineer
Xilinx San Jose
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drjohnsmith
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Thanks @austin

 

I have no problem with what the voltage of the JTAG pins is, 1v8 , 2v5 or 3v3.

 Thats not the question.

 

For reference, I have designed the question out the design , but the question still stands.

 

The background:

 

 

Interfacing a Xilxin FPGA to some 'other' circuit. 

  'Other' circuit is primarily "analog" ,,,

 

Lots of transistors etc, no logic parts.

 

Dont ask.

 

Any way, needed to hook up the FPGA to this, 

   so did 'quick' hack, 

 

BUT

 

As I was not driving or receiving the FPGA JTAG pins with 'logic devices', thought I had better check that I could drive the right voltages ( ViH and ViL ) and would receive the right voltages ( VoH and VoL ), and check the leakage currents etc.

 

Which is where i found I could not find the spec for the JTAG pins,

 

   Yep if I was interfacing to any of the select IO, lots of lovely data 

 

But could not find the data for the JTAG pins. 

 

On assumption that most likely reason was I was looking in wrong places, I asked the forums.

 

As I said above, I have now designed the question out of this design

 

    but I would like to know where the data is for future reference.

 

 

 

 

 

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austin
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Note 4, Table 2 ds892,

 

from page 10 ug570,

 

"The specific configuration mode is selected by setting the appropriate level on the mode
input pins M[2:0]. The M2, M1, and M0 mode pins should be set at a constant DC voltage
level, either through pull-up or pull-down resistors (<1 kΩ), or tied directly to ground or
VCCO_0. The JTAG (boundary scan) configuration interface is always available, regardless of
the mode pin settings."

 

The above paragraph is the summary for all configuration IO (JTAG being the third item in the list of these IO).

 

Easy to find?  Nope, I will grant you that.  Obvious?  Perhaps not.  Documented:  absolutely.

 

VCCO_0 has been the power rail for a long long time for configuration.  Perhaps it has become obvious to us who have used devices over the last 32 years.

 

In any event, there you go:  where it appears, and how it is considered (part of the set of configuration signals).


Another good source of documentation are the boards we build and sell.  The schematics show the details.

 

https://www.xilinx.com/member/forms/download/design-license.html?cid=379171&filename=kcu105-schematic-xtp392.zip

 

Austin Lesea
Principal Engineer
Xilinx San Jose
drjohnsmith
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Thanks Austin

 

I gave up trying to find a Voh and Vol number, 

 

  as you imply, been the same sort of thing for too long, 

     I go back to the 2000 parts...  and just been using,

 

Not worried as to what the power rail is / was,

   just what voltage levels I have to get the inputs to and what I could expect out.

 

I was sort of hoping it would be documented some where like table 9 here is for the select IO pins.

 

https://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf

 

 

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gnarahar
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@drjohnsmith 

 

 Not worried as to what the power rail is / was,

   just what voltage levels I have to get the inputs to and what I could expect out.

 

As I mentioned earlier, you can use the LVCMOS18 specifications mentioned in Datasheet. To further back it up, I would suggest you generate a custom IBIS Model for your part using write_ibis Tcl command and the file will map the JTAG pins to their respective IO Model. 

 

You can use the simulations to determine "what voltage levels I have to get the inputs to and what I could expect out."   

 

I gave up trying to find a Voh and Vol number, 

 

You don't need to give up on the Voh, Vol number yet :)  The IBIS simulations will clarify the information you looking for. 

 

 

- Giri
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drjohnsmith
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Thank you @gnarahar

 

Yes you dd mention that the volts for the select IO pins "SHOULD" be the same as the JTAG  pins earlier, Thank you for that,

   I must be getting old as I try not to design to 'should' or best guess , unless I have to.

 

As for using TCL and getting an IBIS model , and simulating that

   the other extreme, a bit of a hammer to crack a nut ,

    As an engineer, not the best use of my time for a 'simple' JTAG pin voltage VoH and VoL spec,

 

I was just expecting to be able to read a data sheet to find these numbers 

 

As we say

 

La de Dah, As an engineer, I've designed the question out now,

   needed to move on,  I've added more chips to the design, which I know the data sheet for and I have used to drive the JTAG pins.  Had to explain why at design review, as it added extra cost, which although small per board, had to be justified, but there you go,

 

 

 

 

 

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gnarahar
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Registered: ‎07-23-2015

@drjohnsmith 


 Yes you dd mention that the volts for the select IO pins "SHOULD" be the same as the JTAG  pins earlier, Thank you for that,

   I must be getting old as I try not to design to 'should' or best guess , unless I have to.

_____________________________________________________________________________________________________

 

My bad, could have worded it better. Realized it (use of word "should") after seeing this post & backtracked to the post I made.  


 As for using TCL and getting an IBIS model , and simulating that

   the other extreme, a bit of a hammer to crack a nut ,

    As an engineer, not the best use of my time for a 'simple' JTAG pin voltage VoH and VoL spec, 

 


Agree with IBIS simulation being an Overkill. It was just a suggestion in case you had to be spot on with Voh, Vol spec for the Tx/Rx device.  

 


 I was just expecting to be able to read a data sheet to find these numbers 

 

 


Agree. Will take this feedback and send it across. 

 


 La de Dah, As an engineer, I've designed the question out now,

   needed to move on,  I've added more chips to the design, which I know the data sheet for and I have used to drive the JTAG pins.  Had to explain why at design review, as it added extra cost, which although small per board, had to be justified, but there you go, 


Got it. Thanks for the background regarding this query.  
 



   

 

 

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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