Hi. markg@prosensing.com What I've done in order to get this LVDS, is something what you say. I putted an OSERDESE3 and an OBUFDS (code below).
module Serializer(
output OutP, // 1-bit output: Serial Output Data
output OutN, // 1-bit output: Serial Output Data
//.T_OUT(T_OUT), // 1-bit output: 3-state control output to IOB
input CLK, // 1-bit input: High-speed clock
input CLKDIV, // 1-bit input: Divided Clock
input [7:0] D, // 8-bit input: Parallel Data Input
input RST // 1-bit input: Asynchronous Reset
//.T(T) // 1-bit input: Tristate input from fabric
);
// OSERDESE3: Output SERial/DESerializer
// UltraScale
// Xilinx HDL Language Template, version 2018.3
OSERDESE3 #(
.DATA_WIDTH(8), // Parallel Data Width (4-8)
.INIT(1'b0), // Initialization value of the OSERDES flip-flops
.IS_CLKDIV_INVERTED(1'b0), // Optional inversion for CLKDIV
.IS_CLK_INVERTED(1'b0), // Optional inversion for CLK
.IS_RST_INVERTED(1'b1), // Optional inversion for RST
.SIM_DEVICE("ULTRASCALE_PLUS") // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
// ULTRASCALE_PLUS_ES2)
)
OSERDESE3_inst (
.OQ(OQ), // 1-bit output: Serial Output Data
.T_OUT(T_OUT), // 1-bit output: 3-state control output to IOB
.CLK(CLK), // 1-bit input: High-speed clock
.CLKDIV(CLKDIV), // 1-bit input: Divided Clock
.D(D), // 8-bit input: Parallel Data Input
.RST(RST), // 1-bit input: Asynchronous Reset
.T(T) // 1-bit input: Tristate input from fabric
);
// OBUFDS: Differential Output Buffer
// UltraScale
// Xilinx HDL Language Template, version 2018.3
OBUFDS OBUFDS_inst (
.O(OutP), // 1-bit output: Diff_p output (connect directly to top-level port)
.OB(OutN), // 1-bit output: Diff_n output (connect directly to top-level port)
.I(OQ) // 1-bit input: Buffer input
);
// End of OBUFDS_inst instantiation
// End of OSERDESE3_inst instantiation
endmodule
PROBLEMS
1. I need to work in SDR format, but it no longer supports 8:1 serialization factor. So I work in DDR format with Freq/2.
2. There's too much latency between parallel data in and it gets serialized.
The next picture is the lvds implementation making use of Selectio Wizard. As you can see is beautiful and it's very close to my implementation in Ultrascale. The problem is that oserdese2 is not available for Ultrascale.
Details
clock in = 100MHz
SDR mode
1 channel / parallel in 8 bit
clock intern
Do you know any other structure that I could use to obtain the same function of Selectio Wizard's lvds in Ultrascale making use of primitives like oserdese3, bufd..? Thanks in advance.
