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Visitor
Visitor
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Registered: ‎11-12-2020

LVDS High Speed Selectio Wizard

Hi there, currently I'm doing some proves with this ip and basically I want to develop a simple LVDS in which I have 8 bit in parallel to be serialize on one channel (Serialization factor 8 ). It's simple as that, but what I see is a lot of not intuitive configuration that is extremely different in concern to Selectio Wizard.  

do you have any idea of building that simple lvds making use of High Speed Selectio Wizard  ? 

Thanks in advance. 

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Registered: ‎01-22-2015

@Andres2460 

Yes, the SelectIO technology of UltraScale devices is rather complex.  Most of us can make sense of it only by using the High-Speed SelectIO Wizard (HSSW). 

However, if you have a fairly slow source-synchronous interface then you don’t need the HSSW.  In fact, you can look at some of the designs/components that resulted when you used the old SelectIO Wizard and assemble them yourself in the UltraScale device.

Show us one of your old SelectIO Wizard designs that you think might work for this interface.  By “show us”, I mean open the implemented design and shows us a screenshot of the components (eg. BUFIO, IDDR, BUFR, etc).   Also, tell us other details of the interface (clock frequency, DDR or SDR, etc).   Then, we can provide more help.

Cheers,
Mark

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hi @Andres2460 

Did you came across https://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf and https://www.xilinx.com/support/documentation/application_notes/xapp1315-lvds-source-synch-serdes-clock-multiplication.pdf ?

Regards,
Bhushan

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Visitor
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Registered: ‎11-12-2020

Hi. markg@prosensing.com  What I've done in order to get this LVDS, is something what you say. I putted an OSERDESE3 and an OBUFDS (code below). 

module Serializer(
output OutP, // 1-bit output: Serial Output Data
output OutN, // 1-bit output: Serial Output Data
//.T_OUT(T_OUT), // 1-bit output: 3-state control output to IOB
input CLK, // 1-bit input: High-speed clock
input CLKDIV, // 1-bit input: Divided Clock
input [7:0] D, // 8-bit input: Parallel Data Input
input RST // 1-bit input: Asynchronous Reset
//.T(T) // 1-bit input: Tristate input from fabric
);
// OSERDESE3: Output SERial/DESerializer
// UltraScale
// Xilinx HDL Language Template, version 2018.3

OSERDESE3 #(
.DATA_WIDTH(8), // Parallel Data Width (4-8)
.INIT(1'b0), // Initialization value of the OSERDES flip-flops
.IS_CLKDIV_INVERTED(1'b0), // Optional inversion for CLKDIV
.IS_CLK_INVERTED(1'b0), // Optional inversion for CLK
.IS_RST_INVERTED(1'b1), // Optional inversion for RST
.SIM_DEVICE("ULTRASCALE_PLUS") // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
// ULTRASCALE_PLUS_ES2)
)
OSERDESE3_inst (
.OQ(OQ), // 1-bit output: Serial Output Data
.T_OUT(T_OUT), // 1-bit output: 3-state control output to IOB
.CLK(CLK), // 1-bit input: High-speed clock
.CLKDIV(CLKDIV), // 1-bit input: Divided Clock
.D(D), // 8-bit input: Parallel Data Input
.RST(RST), // 1-bit input: Asynchronous Reset
.T(T) // 1-bit input: Tristate input from fabric
);
// OBUFDS: Differential Output Buffer
// UltraScale
// Xilinx HDL Language Template, version 2018.3
OBUFDS OBUFDS_inst (
.O(OutP), // 1-bit output: Diff_p output (connect directly to top-level port)
.OB(OutN), // 1-bit output: Diff_n output (connect directly to top-level port)
.I(OQ) // 1-bit input: Buffer input
);
// End of OBUFDS_inst instantiation
// End of OSERDESE3_inst instantiation
endmodule

PROBLEMS

1. I need to work in SDR format, but it no longer supports 8:1 serialization factor. So I work in DDR format with Freq/2.

2. There's too much latency between parallel data in and it gets serialized. 

The next picture is the lvds implementation making use of Selectio Wizard. As you can see is beautiful and it's very close to my implementation in Ultrascale. The problem is that oserdese2 is not available for Ultrascale. 

Details

clock in = 100MHz

SDR mode 

1 channel / parallel in 8 bit

clock intern

Do you know any other structure that I could use to obtain the same function of Selectio Wizard's lvds in Ultrascale making use of primitives like oserdese3, bufd..? Thanks in advance.

 

Workspace 1_002.png
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Registered: ‎01-22-2015

@Andres2460 

Good start!

On the OSERDES, are you saying that:

   clk_in = CLK = 100MHz?

   clk_div_in = CLKDIV = 12.5MHz?

 

 

 

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Visitor
Visitor
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Registered: ‎11-12-2020

markg@prosensing.com yes, I do, but there's a considerable latency, I don't want it

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Visitor
Visitor
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Registered: ‎11-12-2020

It doesn't work for me, because it's 7 to 1 and i need 8 to 1

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Registered: ‎01-22-2015

Because your 100MHz serialization clock is a slow clock, you can replace the OSERSERE3 with simple Verilog code.

That is, your design simplifies to the following:

  • CLK100:  the 100MHz clock
  • SDAT: a register that you LOC into the IOB
  • OBUFDS: the LVDS output buffer that is fed by SDAT
  • Verilog Serializer
    SDAT_LVDS.jpg

Verilog Serializer: The Verilog Serializer is a Verilog process clocked by CLK100.  Let’s say that you store 8-bits of data to be transmitted in a signal called DATOUT[7 downto 0].  In the Verilog process and on every cycle of CLK100, you do the following:

  • send DAT_OUT[0] to SDAT
  • right-shift by 1 the bits in DATOUT (ie.  DATOUT[6 downto 0] = DATOUT[7 downto 1])

 

Finally, you will need to output CLK100 as part of the SDR output interface.  You can do this by sending CLK100 to pin, C, of an ODDR as shown below.
ODDR_fwd_clock2.jpg

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