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Visitor
Visitor
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Registered: ‎08-01-2017

LVDS clock pair to single ended

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I am working on a FM project using the Zynq UltraScale with AD9361. The FM core is designed using FPGA PL fabric and connect with AD9361 via HPC0 connector. The clock signal is 30MHz which is provided by the Zynq PS. The function of FM core and their connection with the AD9361 have been tested using a 30MHz clock signal generated from Zynq PS. The result is observed at spectrum analyser and it works correctly.    

 

Currently, I like to use a 30MHz LVDS clock coming out from AD9361 for my system rather than PS clock. I read through forums that IBUFDS with BUFG is required for LVDS to single end conversion and my coded of conversion module is attached below. The simulation of the module works correct and the bitstream is successfully generated without any critical warning. However, I can not see the frequency spectrum on the analyser display when I use this LVDS clock. I suspect that the generated single end clock haven't worked with my design and the output data haven't been driven by my AD9361 device. Notice that the source LVDS clock coming out from AD9361 has no problem since it is tested using oscilloscope. Can anyone help me check if my conversion module is okay?

 

My coded of conversion module

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;

 

entity LVDS_2_Single_Clk is
    port (
    aclk_p : in STD_LOGIC;
    aclk_n : in STD_LOGIC;
    aclk_out : out STD_LOGIC
    ); 
end LVDS_2_Single_Clk;

architecture Behavioral of LVDS_2_Single_Clk is
    signal aclk_bufds : STD_LOGIC;

begin
    IBUFDS_INST : IBUFDS
    generic map (
        IOSTANDARD => "DEFAULT")
    port map (
        O => aclk_bufds,    -- Buffer output
        I => aclk_p,        -- Diff_p buffer input (connect directly to top-level port)
        IB => aclk_n        -- Diff_n buffer input (connect directly to top-level port)
        );   
   
    BUFG_INST : BUFG
    port map (
        O => aclk_out,          -- 1-bit output: Clock output
        I => aclk_bufds         -- 1-bit input: Clock input
        );   


end Behavioral;

 

constraint of source clock from AD9361

set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS} [get_ports rx_clk_in_p]           ; ## G6   FMC_HPC0_LA00_CC_P
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS} [get_ports rx_clk_in_n]           ; ## G7   FMC_HPC0_LA00_CC_N

 

My block design of clock conversion

 

block.png

  

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Visitor
Visitor
1,858 Views
Registered: ‎08-01-2017

Re: LVDS clock pair to single ended

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The problem is solved. I change the IBUFDS to IBUFGDS and then it works. I thought the IBUFDS is supported on Vertix but not on Zynq Ultrascale.  

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Mentor
Mentor
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Registered: ‎02-24-2014

Re: LVDS clock pair to single ended

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There's nothing wrong with your clock code, but you haven't addressed the real issue here, which is the clock phase relative to the data going to the AD9361.   Is it possible you aren't getting the spectrum you expect because the data isn't being captured correctly now?    There are multiple methods of configuring the AD9361 interface, and you may need to dig a little deeper into how it's being done.   

Don't forget to close a thread when possible by accepting a post as a solution.
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Visitor
Visitor
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Registered: ‎08-01-2017

Re: LVDS clock pair to single ended

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AD9361's registers are correctly configured and the spectrum is observed when I use a single end clock from the Zynq processor. However, when I use the LVDS clock coming out from AD9361 rather than PS's clock, the spectrum only contains a carrier. Therefore,  I thought the output data haven't been driven by AD9361 and the problem is caused by the clock after LVDS-to-single conversion.  

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Visitor
Visitor
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Registered: ‎08-01-2017

Re: LVDS clock pair to single ended

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The AD9361 is configure by Zynq PS via SPI interface, and the data can be driven when the input clock is provided by PS single end clock. The problem occurs when I replace the PS clock with a LVDS clock generated by AD9361.   

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Visitor
Visitor
1,859 Views
Registered: ‎08-01-2017

Re: LVDS clock pair to single ended

Jump to solution

The problem is solved. I change the IBUFDS to IBUFGDS and then it works. I thought the IBUFDS is supported on Vertix but not on Zynq Ultrascale.  

View solution in original post

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