cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
kastor_yj
Visitor
Visitor
627 Views
Registered: ‎04-16-2019

LVDS input driven by standby driver

Jump to solution

Hi,

I have a design use LVDS input clock which is driven by an ADC. I want to put the ADC into standy mode to save power, but found ADC power off its LVDS driver in standby mode. Then the FPGA's LVDS input buffer get differential signal with input level less than the Vidiff spec, and cause noisy clock during ADC standby period.

How to get a clean LVDS input when the driver is powered off?

Thanks a lot,

Jun

0 Kudos
1 Solution

Accepted Solutions
drjohnsmith
Teacher
Teacher
581 Views
Registered: ‎07-09-2009

LVDS iputs 'oscilating' is a common problem when not being driven,

    this is a good start point

https://www.onsemi.com/pub/Collateral/AN-5046.pdf.pdf

 

TI , also have an app note, AN-1194 I have a print out of,  but the Ti site is down at the moment,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

7 Replies
622 Views
Registered: ‎07-23-2019

I assume "power off the ADC driver" means high impedance.

In that case, some weak pull up/ pull down may sort that out.

0 Kudos
kastor_yj
Visitor
Visitor
618 Views
Registered: ‎04-16-2019

I have tried week pull-up on N node and pull-down on P node. It doesn't help because there is a 100 Ohm termination between P and N. The pull is too weak to generate enough voltage across that 100 Ohm.

0 Kudos
593 Views
Registered: ‎07-23-2019

@kastor_yj 

Sure, you have almost zero between p and n and any noise picked up makes trouble.

What about just one pull-up or pull-down? so you have both lines high or low because of the termination. I think (not sure, though) in that case the receiver won't toggle.

alternatively, have a look at this document, Fig 1-72:

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

 

 

0 Kudos
589 Views
Registered: ‎07-23-2019

I just realized the above is rubbish, is what you did and doesn't work for you...

Then the thing is, if you bias your line and still get false clocks, you are picking up noise, that's the problem.

So the solution would be a neat routing protected from aggressors. Maybe late if you already have a board made...

Couldn't you tie up the ADC enable to a clock enable so you stop any noise clock when the ADC is off?

0 Kudos
drjohnsmith
Teacher
Teacher
582 Views
Registered: ‎07-09-2009

LVDS iputs 'oscilating' is a common problem when not being driven,

    this is a good start point

https://www.onsemi.com/pub/Collateral/AN-5046.pdf.pdf

 

TI , also have an app note, AN-1194 I have a print out of,  but the Ti site is down at the moment,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

572 Views
Registered: ‎07-23-2019

Oh, dear... they need a wall to fix that

0 Kudos
kastor_yj
Visitor
Visitor
532 Views
Registered: ‎04-16-2019

Thanks a lot. This looks good, will modify the PCB to get it implmented. It's a pity the FPGA internal pull-up and pull-down resistor is too weak and can't eliminate the differential noise completely.

0 Kudos