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Adventurer
Adventurer
842 Views
Registered: ‎12-03-2013

LVDS signals query

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Hi All,

 

I have multiple LVDS signal pairs(Tx and Rx) in my design on an Ultrascale + FPGA.

I plan to test performance at 400Mbps using an external loopback . My test setup is giving a fixed pattern output on Tx and then looping in back and checking on Rx. I see that for few signal pairs the received pattern is not same as the transmitted pattern.

 

I am currently using OBUFDS/IBUFDS in my design. I would like to know if this is enough or we need to use any other primitive.

 

Can anyone please help me out with this.

 

Regards

Ayusman

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Adventurer
Adventurer
896 Views
Registered: ‎12-03-2013

Hi,

 

Thanks for the replies.

After debugging found out it was related to hardware issue. Got it fixed and now it is working fine.

 

Regards

Ayusman

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Adventurer
Adventurer
834 Views
Registered: ‎05-23-2018

What is the relation between your Clock and Data? How have you defined that?

 

Are you using source or system synchronous transmission? Do you output the clock through a ODDR or OSERDES or directly? Are you using an IDDR or ISERDES for the input side?

 

Compare xapp585 for a standard use-case using LVDS for video data.

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Teacher
Teacher
824 Views
Registered: ‎07-09-2009

Could be signal errors or could be timing

 

Try slowing the data down to say 10 Mhz, 

  does that work, if so , its likely to be bad termination .

 

If not, its likely to be timing.

 

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Adventurer
Adventurer
897 Views
Registered: ‎12-03-2013

Hi,

 

Thanks for the replies.

After debugging found out it was related to hardware issue. Got it fixed and now it is working fine.

 

Regards

Ayusman

View solution in original post

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