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kkbhagavath
Visitor
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1,387 Views
Registered: ‎02-17-2019

MIO Pin List

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Hi,

Where can I see the dedicated pin name of MIO pins? For ex: I want to check which is TX & RX pins of UART0 among the available MIO pins. My FPGA part no. is XCZU4EG-1SFVC784E.

 

Best regards,

Bhagavath

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tenzinc
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Registered: ‎09-18-2014

@kkbhagavath wrote:

Thanks for your response.

Actually I hsd checked this in the TRM. The doubt I have is about the pin connections in individual interface.

For example: UART pins are mapped to MIO 2 & 3. Which is the TX & RX among these 2 pins? Is this configurable through VIvado Software? 

 

Best regards,

Bhagavath

 


 

-Yes. If you need to know the specific package pin you can find that in the ASCI Pinout or the post implementation IO ports tab. 

 

PS IO bank UART.JPGdf

 

Regards,

T



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4 Replies
1,376 Views
Registered: ‎07-23-2019

 

Any of the MIO pins can be tied to any (low speed) peripheral.

This is defined when you configure your PS in Vivado. IO tab, I think

 

 

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timothyv
Xilinx Employee
Xilinx Employee
1,345 Views
Registered: ‎07-11-2019

Hello @kkbhagavath 

I have included a link to UG1085, which will give you information on the MIO of the Zynq Ultrascale+. Page 783, in particular, has what you are looking for. 

UG1085: https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

I hope this helps! 

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kkbhagavath
Visitor
Visitor
1,287 Views
Registered: ‎02-17-2019

Thanks for your response.

Actually I hsd checked this in the TRM. The doubt I have is about the pin connections in individual interface.

For example: UART pins are mapped to MIO 2 & 3. Which is the TX & RX among these 2 pins? Is this configurable through VIvado Software? 

 

Best regards,

Bhagavath

 

0 Kudos
tenzinc
Moderator
Moderator
1,209 Views
Registered: ‎09-18-2014

@kkbhagavath wrote:

Thanks for your response.

Actually I hsd checked this in the TRM. The doubt I have is about the pin connections in individual interface.

For example: UART pins are mapped to MIO 2 & 3. Which is the TX & RX among these 2 pins? Is this configurable through VIvado Software? 

 

Best regards,

Bhagavath

 


 

-Yes. If you need to know the specific package pin you can find that in the ASCI Pinout or the post implementation IO ports tab. 

 

PS IO bank UART.JPGdf

 

Regards,

T



Don’t forget to reply, kudo, and accept as solution.

Get started FAST with our UltraFAST design methodoly guides and don't forget to visit our Xilinx Design Hubs for additional resources and reference.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs

------------------------------------------------------------------------------------------------

View solution in original post