12-26-2018 05:45 AM
For an MMCM that is configured with feedback and safe mode, we are generating a clk_divide_by_4 and a clk_divide_by_5 outputs. In the simulation we see that phase of the outputs does not align on the first clock outputs, but after some random number of clocks. Is there a way to configure the MMCM so the first (or the known Nth) outputs clocks will be phase align?
12-26-2018 08:49 AM
What does the "first" edge mean? In simulation there is a defined "beginning", but in reality, the starting up of an MMCM is an analog process - there isn't really a concept of the "first" edge.
Is there a way to configure the MMCM so the first (or the known Nth) outputs clocks will be phase align?
So the answer is "you can't".
With your configuration you know that there will be one edge that is aligned between the clocks - every 5th clock of the divide_by_4 and every 4th clock of the divide_by_5 (every 20th clock of the base clock) - but which one it is is harder to figure out.
First, generally, you don't need to know this...
But if you do, I am not sure it is possible with just these clocks - you may also need a clock that represents the common divider - a divide by 20 clock.
The reality is that the MMCM does synchronize all its dividers after it has achieved lock - so the rising edge of the divide_by_20 clock will be the edge in which the divide_by_4 and divide_by_5 align. It is fairly easy to find the phase of a faster clock with respect to a slower clock - take a look at this post for finding the phase of a clock with respect to a slower clock. While the post is old and talks about older technologies, the same idea can be used. Compare your divide_by_4 to your divide_by_20, and your divide_by_5 to your divide_by_20 - each will give you the "first" phase, you really want the "last" phase (since that is the clock period before the edges align) so you need a simple counter to get to the last one.