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immustafad
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Registered: ‎07-23-2019

MYC-C7Z015 DAC Implementation

Hello everybody,

 

I want to implement a dac example into my fpga board (MYC-C7Z015). My input will be 32 bit. First 4 bits are command bit which are C3=0, C2=0, C1=1, C0=1. Next 4 bits are Don't Care Bits. After Don't Care Bits, 12 Bits will be nothing(space). Then the rest 16 bits will be my data.

Now I have an IP with one output port. This Slave Ip has 4 registers. Also I use Zynq-7000 Processing System IP. In each rising edge of Zynq 7000 Processing System IP's clock I look at one bit and assign that bit to my slave register. (in this exapmle slv_reg0). Since my oscilloscope can measure up to 350 Mhz, I have to decrease the frequency of clock. That's why I just do this process in 20 rising edge of clock. In SDK part of my project, I just send some data to my slave register with Xil_Out32 function. However, after all this process the result is considerably different than I expected. My oscilloscope shows the only command bit part. Also this part does not work properly. I expected a really nice square wave. But in the implementation it has some flactuation in the wave. I leave my VHDL code below. Thank you.

 

 

port(
-- Users to add ports here
output : out std_logic := '0';
-- User ports ends
);

-- Add user logic here
process(S_AXI_ACLK)
    variable index : integer := 0;
    variable counter: integer := 0;
    begin
        if rising_edge(S_AXI_ACLK) then
            case index is
-- 4 Command Bits start
when 0 =>
output <= '0';
when 1 =>
output <= '0';
when 2 =>
output <= '1';
when 3 =>
output <= '1';
-- 4 Command Bits end

-- 4 Don't Care Bits start
when 4 =>
output <= '0';
when 5 =>
output <= '0';
when 6 =>
output <= '0';
when 7 =>
output <= '0';
-- 4 Don't Care Bits end

-- 16 Data Bits start
when 8 =>
output <= slv_reg0(16);
when 9 =>
output <= slv_reg0(17);
when 10 =>
output <= slv_reg0(18);
when 11 =>
output <= slv_reg0(19);
when 12 =>
output <= slv_reg0(20);
when 13 =>
output <= slv_reg0(21);
when 14 =>
output <= slv_reg0(22);
when 15 =>
output <= slv_reg0(23);
when 16 =>
output <= slv_reg0(24);
when 17 =>
output <= slv_reg0(25);
when 18 =>
output <= slv_reg0(26);
when 19 =>
output <= slv_reg0(27);
when 20 =>
output <= slv_reg0(28);
when 21 =>
output <= slv_reg0(29);
when 22 =>
output <= slv_reg0(30);
when 23 =>
output <= slv_reg0(31);
-- Data Bits end
when others =>

end case;

if counter = 0 then
index := (index + 1) mod 24;
end if;
counter:= ( counter +1) mod 20;
end if;
end process;
-- User logic ends

 

 

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bruce_karaffa
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Registered: ‎06-21-2017

I may have missed it, but where is a value assigned to slv_reg0?

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immustafad
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Registered: ‎07-23-2019

after export hardware, I open sdk. Via Xillinx_In32 function I can put easily whatever value to specific address. The value of address is taken from xparameters.h. Since  I have only 1 output. This output is equal to address of my slave ip. 

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bruce_karaffa
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Registered: ‎06-21-2017

I assume then that you did not show your complete port definitions.  I suggest putting an ILA inside this module and look at the register.  I would also make count and index signals (or convert them to std_logic_vector signals) and add these to the ILA.

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immustafad
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Registered: ‎07-23-2019

I could not get whay you mean about complete port definitions. I have already defined them in my constraint file. Can you explain a little bit more? 

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bruce_karaffa
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Registered: ‎06-21-2017

I simply meant that this section of the code didn't show all of the ports of the module.

port(
-- Users to add ports here
output : out std_logic := '0';
-- User ports ends
);

I still suggest using an ILA to debug.

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immustafad
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Registered: ‎07-23-2019

Rest of the ports are defiined by axi peripheral ip in the module. 

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