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joe306
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Registered: ‎12-07-2018

Max Distance for JTAG Connector and Ultrascale+ MPSOC

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Hello, I checked the TRM for the Ultrascale devices but I did not see any guidance on the maximum distance the JTAG connector can be from the FPGA. Can anyone help me find the document that has the distance please.

 

Thank you

Joe

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Registered: ‎01-22-2015

Joe,

The reference I gave you suggests a distance of less than 10cm from JTAG connector to FPGA at the fastest frequency for JTAG TCK.   You can also look at boards made by Xilinx to see how closely they have placed the JTAG connector to the FPGA.

Make this distance a priority when laying out your board.  I'm sure you can get the JTAG connector and FPGA closer than 10cm. 

If you have already made a board where the JTAG-to-FPGA spacing is too large and things are not working - then, you should be able to lower the JTAG TCK frequency to get things working again.

See page 43 in UG908(v2020.2) for instructions on using Vivado to control the JTAG TCK frequency.

Cheers,
Mark

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watari
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Registered: ‎06-16-2013

Hi @joe306 

 

What is the target frequency of TCK ?

Max distance for JTAG connector depends on the target frequency of TCK.

 

Best regards,

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Registered: ‎01-22-2015
joe306
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Registered: ‎12-07-2018

Hello, I am using the Platform Cable USB II and I don't know where in Vivado the TCK is set. I'll try to find that in https://www.xilinx.com/support/documentation/data_sheets/ds593.pdf.

 

Thank you

Joe

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joe306
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Registered: ‎12-07-2018

Hello, I beleve the default is 6Mhz.

Joe

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joe306
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Registered: ‎12-07-2018

Hello, page 28 of DS539.pdf has:

If the target system has only one programmable device, the 2 mm connector should be located as close as possible to the target device.

I only have one FPGA on my PCB.

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384 Views
Registered: ‎01-22-2015

Joe,

The reference I gave you suggests a distance of less than 10cm from JTAG connector to FPGA at the fastest frequency for JTAG TCK.   You can also look at boards made by Xilinx to see how closely they have placed the JTAG connector to the FPGA.

Make this distance a priority when laying out your board.  I'm sure you can get the JTAG connector and FPGA closer than 10cm. 

If you have already made a board where the JTAG-to-FPGA spacing is too large and things are not working - then, you should be able to lower the JTAG TCK frequency to get things working again.

See page 43 in UG908(v2020.2) for instructions on using Vivado to control the JTAG TCK frequency.

Cheers,
Mark

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drjohnsmith
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Registered: ‎07-09-2009

JTAG is an industrial standard,

  It has no defined frequency , it can run from KHz to the max frequency yourdevices / board can work at 

I have used 25 Mhz JTAG and have had systems that can only run at KHz.

 

JTAG is a "simple" serial link,

have look here for a basis

https://www.xjtag.com/about-jtag/design-for-test-guidelines/

I would strongly suggest that you always put a buffer on the board for the JTAG lines,

    and observe the termination for the speed you want to run at.

The buffer on the JTAG , a simple 244 or similar, 

      it isolates the board from the possible long cables to the JTAG pod, as well as some ESD isolation, much better to blow a 244 than the FPGA.

 

   

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joe306
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Registered: ‎12-07-2018

Hello, thank your for responding to my post. The board is in layout now and I will make sure the connector is below 10cm.

Thank you

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joe306
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Registered: ‎12-07-2018

Thank you very much for responding to my message. I will do that on my next design.

Joe

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