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Registered: ‎05-30-2019

Multi Tile/Channel Synchronization in RF SoC 1275

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Hello everyone,
 
I am facing some issues with performing the multi-tile synchronization on my ZCU 1275 RF SoC. Coming to the details, I am building a project where I need 8 DACs, which corresponds to 2 data converter tiles on the RF SoC architecture (each tile contains 4 DACs and a driving clock). The driving clock for each tile is 2.048 GHz generated from the external hardware clock module that contains 3 PLL sources. The clock inputs of the two tiles under consideration are connected to 2 PLL sources. However, I found out that for the DAC outputs for both tiles to be in-phase, we need to perform multi-tile synchronization. I am following the PG269 document for this. The multi-tile synchronization (MTS) feature enables multiple converter channels working with an aligned and deterministic latency across tiles and chips. I could enable this feature for the "Data-converter" IP that I am using in my design. Enabling this further adds a pin "user_sysref_dac," which is a PL SYS Reference input. The "PG269 RF SoC Data converter user guide" gives a set of guidelines to perform the MTS from pages 169-177. And primarily, the SYSREF frequency must meet the following requirements as given :
  1. If synchronizing RF-ADC and RF-DAC tiles with different sample frequencies, the frequency must be an integer submultiple of GCD(DAC_Sample_Rate/16, ADC_Sample_Rate/16)
  2. SYSREF must also be an integer submultiple of all PL clocks that sample it. This is to ensure the periodic SYSREF is always sampled synchronously.
  3. Less than 10 MHz
I get 8 MHz as SYSREF frequency for my design with 2048 MHz as my DAC_sample_Rate following the above instructions. I generated this 8 MHz reference signal using the "CLOCKING_WIZARD IP" from the 300 MHz LVDS oscillator. This is passed through a register driven by the PL clock before being connected to the "user_sysref_dac" pin of the data converter IP as described in the document. But after enabling this MTS feature and performing the above extra steps, the timing fails; I should be doing something wrong, so I will appreciate it if I can get some help with this. 
I have attached the PG269 document, my Vivado project, and the schematic, and the error message that I receive.

Please let me know if you have any further questions. Thank you very much!
 
Regards
Sravan
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MTS_timing_error.PNG
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klumsde
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298 Views
Registered: ‎04-18-2011

The first problem I see is that the PL sysref is not managed properly

 I generated this 8 MHz reference signal using the "CLOCKING_WIZARD IP" from the 300 MHz LVDS oscillator. 

This is not allowed. This should come from the same place as the Analog SYSREF. 

you should use the CLK103 card, otherwise known as the RF super clock module.

This guide shows how to test 16x16 MTS on the 1275. It talks about using the CLK103 to create the clocks and SYSREF for MTS.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/63864883/ZCU1275+ZCU1285+RFSoC+16X16+MTS+Design+Getting+Started+Guide

 

Keith 

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klumsde
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299 Views
Registered: ‎04-18-2011

The first problem I see is that the PL sysref is not managed properly

 I generated this 8 MHz reference signal using the "CLOCKING_WIZARD IP" from the 300 MHz LVDS oscillator. 

This is not allowed. This should come from the same place as the Analog SYSREF. 

you should use the CLK103 card, otherwise known as the RF super clock module.

This guide shows how to test 16x16 MTS on the 1275. It talks about using the CLK103 to create the clocks and SYSREF for MTS.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/63864883/ZCU1275+ZCU1285+RFSoC+16X16+MTS+Design+Getting+Started+Guide

 

Keith 

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278 Views
Registered: ‎05-30-2019

Hi Keith,

Thank you very much for your suggestions. I will go through it.

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