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Voyager
Voyager
483 Views
Registered: ‎04-12-2012

Multiple IDELAYE3s with a single IDELAYCTRL

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Hello,

I understand that when using IDELAYE3 in Component Mode we should instantiate only one "IDELAYCTRL" component in the top level of the design.
And according to UG571 IDELAYCTRL should be driven with the same clock as the IDELAYE3 component.

This raises a question:
Suppose my design has multiple LVDS channels (synchronous to different clocks) and more then one requires the usage an IDELAYE3.
With what clock should the single IDELAYCTRL component be driven ?

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Moderator
Moderator
430 Views
Registered: ‎08-08-2017

Hi @shaikon 

As you know The REFCLK_FREQUENCY attribute  of the IDELAY component must reflect the clock frequency applied to the
IDELAYCTRL component.

You  can have the REFCLK_FREQUENCY in the range of 300MHz to 800 Mhz.

Capture.JPG

The reference frequency to the IDELAYCTRL is not depends on interface speed .

Unlike 7 Series the Tap size is not impacted by the REFCLK_FREQUENCY and the resolution is over PVT.

so the conclusion is that you can have only one IDELAYCTRL in the design for different inteface speed. only make sure that REFCLK frequency attribute is set to same value for all the IDELAYE3 instances which  mimic the clock frequency
applied at the IDELAYCTRL

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post

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Scholar
Scholar
472 Views
Registered: ‎08-07-2014

@shaikon,

Not sure, but I think there should be an IDELAYCTRL  for every individual clock.

------------FPGA enthusiast------------
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Voyager
Voyager
452 Views
Registered: ‎04-12-2012
Can someone please confirm this ?
Or provide another answer
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Highlighted
Moderator
Moderator
431 Views
Registered: ‎08-08-2017

Hi @shaikon 

As you know The REFCLK_FREQUENCY attribute  of the IDELAY component must reflect the clock frequency applied to the
IDELAYCTRL component.

You  can have the REFCLK_FREQUENCY in the range of 300MHz to 800 Mhz.

Capture.JPG

The reference frequency to the IDELAYCTRL is not depends on interface speed .

Unlike 7 Series the Tap size is not impacted by the REFCLK_FREQUENCY and the resolution is over PVT.

so the conclusion is that you can have only one IDELAYCTRL in the design for different inteface speed. only make sure that REFCLK frequency attribute is set to same value for all the IDELAYE3 instances which  mimic the clock frequency
applied at the IDELAYCTRL

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post