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Explorer
Explorer
498 Views
Registered: ‎01-18-2011

Need for reset the PLL during native mode reset sequence

Hello

 

UG571: To apply a reset: 

1. Assert reset to the PLL.

2...
 

Is it obligatory? What for? Can I stop the CLKOUTPHY high-speed clock only instead of reset the entire PLL?

Is it obligatory to reset and MMCM too, if I generate APP_CLK and RIU_CLK from MMCM, not from PLL?
 

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Scholar jmcclusk
Scholar
473 Views
Registered: ‎02-24-2014

Re: Need for reset the PLL during native mode reset sequence

From UG571:

 

When an application is running in an FPGA, apply the following steps to safely reset the application and allow a correct bring-up afterward:

 

Apply Reset

To apply a reset:

1. Assert reset to the PLL.

2. Apply reset to RXTX_BITSLICE.TX_RST_DLY, RXTX_BITSLICE.RX_RST_DLY, TX_BITSLICE_TRI.RST_DLY, RXTX_BITSLICE.TX_RST, RXTX_BITSLICE.RX_RST, TX_BITSLICE_TRI.RST, and/or BITSLICE_CONTROL.RST.

3. Stop strobe clocks.

4. Wait the minimum PLL reset assertion time before releasing the reset. For this timing specification, consult the PLL section of the UltraScale device data sheets [Ref 2]. Then follow the steps in Native Mode Bring-up and Reset, page 299 for correct bring-up

Don't forget to close a thread when possible by accepting a post as a solution.
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