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chenji.tu
Observer
Observer
8,565 Views
Registered: ‎02-04-2016

Need tutorial for Zynq UltraScale+ in Vivado 2015.4

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Dear community,

 

I am looking for a tutorial similar to UG940, but for Zynq UltraScale+ ZU2EG.

 

I need to connect the ARM to PL and drive the logics in FPGA from ARM. But I have no idea how to start. There are some tutorial for Zynq 7, but the chip for our project is Zynq UltraScale, and I can't find a tutorial for it.

 

Please help.

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austin
Scholar
Scholar
14,884 Views
Registered: ‎02-27-2008

c,

 

As the Zynq MPSoC is so new, and we are updating documents right now, contact your local Xilinx distributor, or Xilinx FAE for help.  They have materials in advance of the finished documents to help you and will advise you of when new documents are scheduled for delivery (there is a schedule).

 

Generally speaking design in MPSoC Zynq with Vivado is similar to 7000 series Zynq, but the MPSoC is more complex, and there are new choices to make.

Austin Lesea
Principal Engineer
Xilinx San Jose

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austin
Scholar
Scholar
14,885 Views
Registered: ‎02-27-2008

c,

 

As the Zynq MPSoC is so new, and we are updating documents right now, contact your local Xilinx distributor, or Xilinx FAE for help.  They have materials in advance of the finished documents to help you and will advise you of when new documents are scheduled for delivery (there is a schedule).

 

Generally speaking design in MPSoC Zynq with Vivado is similar to 7000 series Zynq, but the MPSoC is more complex, and there are new choices to make.

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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trenz-al
Scholar
Scholar
8,483 Views
Registered: ‎11-09-2013

ZU2EG will not be available in 2016, so if that is your interest you have plenty of time.

 

right now you can work with ZU9EG if you have early access license.

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chenji.tu
Observer
Observer
8,395 Views
Registered: ‎02-04-2016

Hello @trenz-al

 

I already have early access license. Right now I have to determine the IO pin assignment for other PCB design team, so they can start the PCB design for ZU2EG.

 

I have a list of IOs, created an IO planning project and migrated to RTL project in Vivado 2015.4.1. But I have no idea from there. How can I connect clock and reset from ARM to the user logic in PL? Please advice.

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trenz-al
Scholar
Scholar
8,389 Views
Registered: ‎11-09-2013

zu2eg pinouts are fixed that is no problem, you can start design now

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