Optimal Mid-cycle Clock Production

[chsdkj]

When a need arises for clocking a primitive (such as a BRAM, a URAM, a DSP, or etc.) in the middle of a clock cycle, it would seem that there are three ways to proceed:

a) use of an inverter (or specification of use of a built-in clock-inversion option (if provided)) for the main clock being presented at the primitive's clock input;

b) use of an MMCM or PLL to produce a first main clock, with its complementary output as the second clock;

c) use of an MMCM or PLL to produce a first main clock, with a 180-degree phase-shifted version of the clock as the second clock.

Information would be appreciated on which approach would tend to produce the highest-quality second clock, i.e., a maximally-optimally-placed rising edge in the middle of the cycle, along with reasonably-optimal (~50%) duty cycle.

[jg_bds]

For such as general a question as this, I'd say a).

-Joe G.

[chsdkj]

Thanks, but I'd want/expect a Xilinx employee to answer the inquery, who would hopefully provide a somewhat detailed discussion of the up- and down-sides of each approach.

[ratter · Accepted solution]

I would recommend using the clocking wizard to generate an MMCM and have 2 output clocks with the same frequency, one clock output with 0 degree phase shift and the other with 180 degree phase shift.

There are several benefits to this method.

Constraints will be generated for both output clocks.

The tools can time the clock crossing between these 2 clocks if they cross.

Each clock can be used to generate it's associated control signals, giving you the entire clock period for the signals to meet timing at the destination.