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ninjanymo
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Registered: ‎09-10-2018

PCB with no DDR. What to do with the different DDR pins?

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UG933 explains that VCCO_DDR should be tied to VCC_PAUX, while PS_DDR_VREF0/1 and PS_DDR_VRN/P should be left floating, which is fine.

 

Further, UG933 describes what to do with unused I/O pins in Table 5-5:

t_5_5.PNG

However, it seems as if Table 5-5 describes what to do with unused DDR I/O if some of them are used. In my use-case, none of them are used and that get's me confused when there are different guidelines for no-ECC and ECC.

 

So just to make sure:

Can I leave all DDR pins floating while enabling internal pull-ups on the pins described as I/O by Table 5-4 in UF933?

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gnarahar
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Registered: ‎07-23-2015

@ninjanymo 


Can I leave all DDR pins floating 


Yes, if you are not using the PS DDR, leave the pins unconnected except for VCCO_DDR which is tied to VCCPAUX as mentioned in UG933 v1.13

- Giri
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gnarahar
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@ninjanymo 


Can I leave all DDR pins floating 


Yes, if you are not using the PS DDR, leave the pins unconnected except for VCCO_DDR which is tied to VCCPAUX as mentioned in UG933 v1.13

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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ninjanymo
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Registered: ‎09-10-2018
Great, thanks.
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ninjanymo
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Registered: ‎09-10-2018

I realized that I asked this in the wrong board (UltraScale architecture).

 

I am working with the Zynq-7000. Is it safe to assume that your answer still stands for that architecture?

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gnarahar
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Registered: ‎07-23-2015

@ninjanymo Yes, it still stands since the discussion was around UG933 which is the PCB design guide for Zynq-7000 device :) 

- Giri
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There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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rlindner3
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Registered: ‎02-19-2019

My application is an Ultrascale, specifically an XCZU3EG-SFVC784 and will not be using any DDR.

But VCCO_PSDDR is constrained to 1.5V where VCCAUX or VCC_PSAUX are 1.8V.

I am guessing these would not want to be connected. 

So, I need to know what to do with VCCO_PSDDR, VCC_PSDDR_PLL and VCC_PSINTFP_DDR to use the least possible quiescent power.

Thanks - Robert L

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gnarahar
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Registered: ‎07-23-2015

@rlindner3  This is an already closed thread and generally it is good to post your query in a new thread to gain traction and not get missed in the community. 


So, I need to know what to do with VCCO_PSDDR, VCC_PSDDR_PLL and VCC_PSINTFP_DDR to use the least possible quiescent power.


You can tie these pins to GND if DDR is not used. Please use XTP427 Schematic checklist and UG583 during your schematic and PCB design 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
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rlindner3
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Registered: ‎02-19-2019

Thanks.

FMI - How can I tell whether a thread is closed.

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gnarahar
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Registered: ‎07-23-2015

@rlindner3 


FMI - How can I tell whether a thread is closed.


If the thread has an Accepted Solution. New posts made on these threads tend to get missed since the community sees the thread has a solution and may not look into it. 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
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