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m006
Voyager
Voyager
7,890 Views
Registered: ‎03-18-2008

PCIe Gen1-->Gen3 negotiation for ultrascale GTHE3

The PLL switch is implemented by DRP configuration for 7 series GTHE2

 

but ,it seems that the  ultrascale GTHE3 doesn't use DRP control FSM.

 

how to implement the PLL ration dynamic change?

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venkata
Moderator
Moderator
6,900 Views
Registered: ‎02-16-2010

in 7-series GTH, CPLL does not support Gen3 speed so QPLL needed to be used. In UltraScale, CPLL can support Gen3 speed also. So PLL switch is not necessary.
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