07-13-2020 08:51 PM
I my design I am using an Ultrascale+ SoC. I have instantiated the PL system monitor and configured it as shown here:
With my design loaded, if I open the hardware manager, I can successfully view data coming in from the PS System Monitor. All readings seem to be active, as they fluctuate as it is expected:
However, if I open the PL System Monitor, all the readings seem to be frozen, the temperature is stuck at the minimum possible and all Voltage readings are stuck at 0.0V:
Moreover, I have hooked up ILA probes to the PL System Monitor and I see that the core is always BUSY. This is also visible by reading the status register (address 0x4) from the AXI-Lite bus.
I have tried everythink I could think of, I have changed the settings both from JTAG and from the AXI bus, I have reset the core, I have changed clock dividers, sequence settings, adquisition modes, averaging modes, etc, basically anything that I thought could be to blame, but I have had no success.
What can I be missing here? What could cause the core to just go into BUSY and stay there forever? I am assuming this is not normal, right?
In the core's configuration I have enabled the temperature channel in the second tab. With the configuration from the first tab pasted above and that, shouldn't the temperature reading just work right after flashing the bitstream?
07-14-2020 02:56 PM
Are you sure it is getting the 100Mhz clock you specify in the System Management Wizard?
I've seen before that you can lock up the ADC interface if the DCLK is much slower than the JTAG clock
07-15-2020 04:45 PM
Ok never mind, it turns out this is a faulty board. I have tested the same design in another board and it works fine.... I guess the XADC was somehow burned or something on this device...