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Observer richnsim
Observer
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Registered: ‎06-01-2018

PL not reset during POR

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Dear Community

I’m using a Zync Ultrascale+ MPSoC (XCZU6EG).

When I assert the PS_POR_B pin, I noticed, that PS would stop working immediately (as expected), but PL would continue normal operation, until I de-assert the PS_POR_B pin (unexpected).

To better illustrate the situation, I took a snapshot of my oscilloscope:

POR_Verhalten_FlipFlop_bearbeitet_2.png

- The red signal shows, that the reset signal "pl_resetn0" from the MPSoC does not get asserted during the POR!
- The blue signal shows some logic output, clocked by an external clock signal that is also not affected by the POR!
- Only the green line shows a clock signal derived from PL Fabric Clock – PL0, which is reset during POR.

In the Technical Reference Manual (page 1126) it says:
“External POR => Resets all logic, RAMs, and registers.”

- Is it expected behavior, that PL is not reset while POR is asserted?

- Is there a way to reset the PL while POR is asserted?

 

Thanks for your help,
Simon

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1 Solution

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407 Views
Registered: ‎09-17-2018

Re: PL not reset during POR

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Yes,

PS_POR_b only resets the PS.  Often in a complex system, the software requires a restart while allowing the programmable hardware to continue function.  Obviously if the PL uses clocks or signals from the PS, such a restart doesn't make much sense.  Separating a portion of the PL to not use any PS signals is required for that section to continue uninterrupted whe a PS_POR_b is asserted.

To reset the entire device, PL and PS, PROG_b is used -- or remove power from Vccint, Vccaux, or Vcccfg (any one of those supplies will trigger a loss of power, requiring a power on reset and restart).

l.e.o.

 

 

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2 Replies
408 Views
Registered: ‎09-17-2018

Re: PL not reset during POR

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Yes,

PS_POR_b only resets the PS.  Often in a complex system, the software requires a restart while allowing the programmable hardware to continue function.  Obviously if the PL uses clocks or signals from the PS, such a restart doesn't make much sense.  Separating a portion of the PL to not use any PS signals is required for that section to continue uninterrupted whe a PS_POR_b is asserted.

To reset the entire device, PL and PS, PROG_b is used -- or remove power from Vccint, Vccaux, or Vcccfg (any one of those supplies will trigger a loss of power, requiring a power on reset and restart).

l.e.o.

 

 

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Observer richnsim
Observer
356 Views
Registered: ‎06-01-2018

Re: PL not reset during POR

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Dear @lowearthorbit

Thanks for your reply. Using PROG_b seems to do the trick. Unfortunately on my purchased SoM (system on module) I don't have this signal available. 

The workaround I currently use is to instantiate a PLL in the PL and monitor the "clk_stopped" signal which tells me, when the PS is in reset.

Though I was hoping to find a "prettier" solution.

Simon

 

 

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