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338 Views
Registered: ‎10-25-2019

PLL IP in Xilinx Vivado

Hello,

I am using Zedboard for this experiment.

I am trying to use PLL IP to generate 100MHz clock by providing clk_in1 as 20MHz. Then use this 100MHz in another module. So, I am confused about how to use it. I have few questions,

1. In clocking wizard, I select PLL and then provide the value of clk_in1 as 20 and clk_out1 as 100. So, do I need to do Generate output products as Out-of-context module or Global ?

2. And how to write the constraint file if I want to generate the bitstream it will need pin location for all I/O ports then clk_in1 has to be connected to which pin location? We cannot connect it to Y9 (clk pin of Zedboard) because it is 100MHz.

Currently, I have written a create_clock constraint to generate 20MHz but to generate bitstream we have to provide the location of clk_in1 so what should I provide?

Regards,
Shivani Shah

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4 Replies
pthakare
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Moderator
314 Views
Registered: ‎08-08-2017

Hi shivani.shah@iiitb.org 

You need a 20MHz reference clock input ,

So wanted to check what is the source of 20MHz reference clock input (clk_in1)?

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245 Views
Registered: ‎10-25-2019

Hello @pthakare,

Thanks for your response.
 
Yes, how to provide the source for 20MHz reference clock input (clk_in1) and while writing pin location what should I write, because Bitstream will not generate if I don't provide a pin location to any I/O port.

I also found this link, but not sure how to use it.
https://www.xilinx.com/support/answers/62488.html 

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pthakare
Moderator
Moderator
242 Views
Registered: ‎08-08-2017

Hi shivani.shah@iiitb.org 

You should have clock source providing 20Mhz on the board and output routing to clock capable pin of FPGA.

If so , you need check on what FPGA pin the clock is coming and write the location constraint/IOSTANDARD constraints based on it

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209 Views
Registered: ‎10-25-2019

Hi @pthakare,

Ok, I will check for the pin on board providing me 20MHz and then try to work around that.

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