[Place 30-716] 2016.2 Virtex UltraScale - Clock placement error when driving 1 MMCM from one global clock port

[justinz]

[Place 30-716] Sub-optimal placement for a global clock-capable IO pin-BUFGCE-MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets u_tp9001_wop/u_clk_top/u_mac_pll/clk_ref_in] > u_tp9001_wop/u_clk_top/u_mac_pll/u_clk_ref_in (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y96 (in SLR 0) u_tp9001_wop/u_clk_top/u_mac_pll/u_mmcme3_base (MMCME3_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME3_ADV_X0Y2 (in SLR 0) The above error could possibly be related to other connected instances. Following is a list of all the related clock rules and their respective instances. Clock Rule: rule_gclkio_bufg Status: PASS Rule Description: An IOB driving a BUFG must use a GCIO in the same clock region as the BUFG u_clk_mac/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y231 (in SLR 0) u_tp9001_wop/u_clk_top/u_mac_pll/u_clk_ref_in (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y96 (in SLR 0) Clock Rule: rule_bufgce_bufg_conflict Status: PASS Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be used at the same time u_tp9001_wop/u_clk_top/u_mac_pll/u_clk_ref_in (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y96 (in SLR 0) Clock Rule: rule_mmcm_bufg Status: PASS Rule Description: A MMCM driving a BUFG must be placed in the same clock region of the device as the BUFG u_tp9001_wop/u_clk_top/u_mac_pll/u_mmcme3_base (MMCME3_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME3_ADV_X0Y2 (in SLR 0) u_tp9001_wop/u_clk_top/u_mac_pll/u_clk_fb_in (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y71 (in SLR 0) Clock Rule: rule_bufgce_bufg_conflict Status: PASS Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be used at the same time u_tp9001_wop/u_clk_top/u_mac_pll/u_clk_fb_in (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y71 (in SLR 0) Clock Rule: rule_bufgce_bufg_conflict Status: PASS Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be used at the same time and u_tp9001_wop/u_clk_top/u_mac_pll/u_clk_out0 (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y70 (in SLR 0)

how to locate the mmcm in the same clock region with drive clock port?

[pthakare]

Hi @justinz

The GC Pin pairs in each bank have direct access to the MMCM's and PLLs that are in the CMT adjacent to the same I/O bank.

The normal behavior is  that Input clock ports connected to the MMCM  inputs are automatically placed in the same clock region.

Can you please let us know the complete VU part number and which pin is used to bring the clock onto the device ?

Additionally refer the pass rule description in error message to check if you are no violating any of the condition.

----------------------------------------------------------------------------------------------------------------------------

Reply if you have any queries, Give Kudos and Accepts as solution if you get one

-----------------------------------------------------------------------------------------------------------------------------

[justinz]

The FPGA is VU440FLGA2892  

The used GC port pair are : AJ48,AJ49

[pthakare]

Hi @justinz

Corrects pins are being used.

Are you driving two MMCMs from the same port?  if so add CLOCK_DEDICATED_ROUTE BACKBONE constraint on MMCM input clock pin in constraint file.

Refer to this AR related to the same error.

https://www.xilinx.com/support/answers/64175.html

--------------------------------------------------------------------------------------------------------------------------------------------------------------------

If you are following all the condition and still getting this error , personally mail me your project file or  synth .dcp to check the Clocking in your design

--------------------------------------------------------------------------------------------------------------------------------------------------------------------

[justinz]

    the GC pair ports only drive one mmcm. here is diagram of the clk strcuture.

   BTW，my  synth.dcp is over 640M , how do I send it to you?

[pthakare · Accepted solution]

Hi @justinz

I have analysed the post synthesis schematic, the CLK1 is driving two MMCM's in the design.

To demote  the error message you are getting because of this clocking topology add the BUFG after IBUFDS and apply  CLOCK_DEDICATED_ROUTE constraints for the net driven by the BUFG to ANY_CMT_COLUMN

The CLOCK_DEDICATED_ROUTE constraint is typically used when driving from a clock buffer in one clock region to an MMCM or PLL in another clock region.refer to the page 94 for detailing of this constraint. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug949-vivado-design-methodology.pdf  

---------------------------------------------------------------

Give Kudos and accept as solution

---------------------------------------------------------------

[justinz]

Hi, pthakare

                  clk1 is drives 2 mmcms as red color shows, clk2 only drives 1 mmcm (u_mac_pll) 

               why the error message always point to the u_mac_pll which driven by clk2?

[justinz]

the err message printscr