cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
inigomonge
Visitor
Visitor
777 Views
Registered: ‎05-09-2019

Power loss in voltage rail in ZU27

Jump to solution

Hello,

I am working in a project and we are using the XCZU27DR-L2. Because this project is supposed to be sent to space there is a big possibility that sometimes one of the power supplies will clamp to around 0.9V. The main strategy to fix this is to detect this problem and turning off and on that voltage. In theory the core voltages of 0.72V and 0.85V should be safe from this problem.

If one of the voltages clamps (let's say 1.2V, 1.8V or 3.3V for example), can we just power off and on that line or do we have to repower the whole FPGA so it keeps working properly?

Thank you in advance.

Best regards

Inigo

Tags (3)
0 Kudos
1 Solution

Accepted Solutions
tenzinc
Moderator
Moderator
721 Views
Registered: ‎09-18-2014

No need to go through another whole power sequene. Depending on the rail, turning the rail off and on shoud be fine but I would highly recommend reconfiguration to reinitialize the device. I assume while clamping the logic and data inside the device pertaining to the clamped rail may not be reliable. 



Don’t forget to reply, kudo, and accept as solution.

Get started FAST with our UltraFAST design methodoly guides and don't forget to visit our Xilinx Design Hubs for additional resources and reference.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs

------------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
4 Replies
tenzinc
Moderator
Moderator
722 Views
Registered: ‎09-18-2014

No need to go through another whole power sequene. Depending on the rail, turning the rail off and on shoud be fine but I would highly recommend reconfiguration to reinitialize the device. I assume while clamping the logic and data inside the device pertaining to the clamped rail may not be reliable. 



Don’t forget to reply, kudo, and accept as solution.

Get started FAST with our UltraFAST design methodoly guides and don't forget to visit our Xilinx Design Hubs for additional resources and reference.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs

------------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
klumsde
Moderator
Moderator
700 Views
Registered: ‎04-18-2011

@inigomonge 

if you clamp the VCCAUX rail to the 0.9V then you you will likely lose the PL configuration... 

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
inigomonge
Visitor
Visitor
694 Views
Registered: ‎05-09-2019

I see. So from what I read from you the best answer is to power off the whole FPGA  and then on again.

Thank you.

0 Kudos
klumsde
Moderator
Moderator
689 Views
Registered: ‎04-18-2011

Yes.

I expect losing the AUX rail on the PS is going to require the PLLs to re-lock etc. 

Safest is to reboot. 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------