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Observer
Observer
1,298 Views
Registered: ‎09-21-2018

Pull-up resistors on Zynq MPSoC SPI interface MISO, MOSI signals

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I am using the xtp427 ultrascale-plus schematic review checklist to review my Zynq US+MPSoC schematic.  The checklist says to place 2.0kohm pull-up resistors on the SPI MISO and MOSI signals near the SPI device (with no other explanation).  I cannot find any other Xilinx documents that recommend a pull-up on MISO, MOSI.  For example, UG583 pg 178 recommends pull-ups on SPI SS pins, but no mention of pullups on MISO, MOSI.  We are interfacing to a Cypress QSPI Flash (S25FL256) which also has no recommendation for pull-ups on MISO, MOSI.  Are these pull-ups really required?  And if so why?

Thanks, Ted

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Scholar
Scholar
1,273 Views
Registered: ‎02-01-2013

 

Oddities like this recommendation are generally the response to unexpected operation in the absence of the recommended action. Since the SPI interface can be operated as a master or a slave, it is likely that the circuitry can get confused if the MOSI and/or MISO lines are not pulled high at some point during system operation.

If you wait long enough, you might get a more-official response like this:

     https://forums.xilinx.com/t5/7-Series-FPGAs/PS-MIO-SPI-pull-ups/m-p/902053

-Joe G.

 

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Scholar
Scholar
1,274 Views
Registered: ‎02-01-2013

 

Oddities like this recommendation are generally the response to unexpected operation in the absence of the recommended action. Since the SPI interface can be operated as a master or a slave, it is likely that the circuitry can get confused if the MOSI and/or MISO lines are not pulled high at some point during system operation.

If you wait long enough, you might get a more-official response like this:

     https://forums.xilinx.com/t5/7-Series-FPGAs/PS-MIO-SPI-pull-ups/m-p/902053

-Joe G.

 

View solution in original post

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Observer
Observer
1,240 Views
Registered: ‎09-21-2018

Thank you very much Joe.  I will include the resistors in my design.

-Ted

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