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Adventurer
Adventurer
2,760 Views
Registered: ‎04-01-2008

Question about Kintex Ultrscale HR Bank @ 1.8V, outputting LVDS signals ...

I searched the message board, and found similar questions, but no definitive answer. 

I have a design that is using a KU035, 1156 package, and BANK 64 is set to 1.8V VCCO.  I have outputs that are both LVCMOS18 and LVDS, and inputs that are at 1.8V.  When I use the LVDS IOSTANDARD for this bank, Vivado gives me an error saying its not a valid IO Standard, use LVDS_25. 


My question is, can I leave the VCCO at 1.8V, and set all of the IOSTANDARDS to be 2.5V (LVCMOS25 and LVDS_25), and have the FPGA transmit and receive data correctly? 

 

Thanks for the help.
jechambe

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4 Replies
Community Manager
Community Manager
2,708 Views
Registered: ‎08-08-2007

Re: Question about Kintex Ultrscale HR Bank @ 1.8V, outputting LVDS signals ...

Bank 64 is a XCKU065-FFVA1156 is a HR bank, the IOSTANDARD LVDS can only be used in HP banks and IOSTANDARD LVDS_25 is used for banks HR.

Described : https://www.xilinx.com/support/documentation/user_guides/ug571-ultrascale-selectio.pdf

Table 1-55: Allowed Attributes for the LVDS I/O Standards.

 

In UG571 Table 1-77  is the VCCO and VREF Requirements for Each Supported I/O Standard and for LVDS_25 outputs the Vcco must be 2.5V. 

It is definitely not recommended to power the Vcco at 1.8V on the board while setting the IOSTANDARD to the 2.5V in software. 

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Adventurer
Adventurer
2,563 Views
Registered: ‎04-01-2008

Re: Question about Kintex Ultrscale HR Bank @ 1.8V, outputting LVDS signals ...

So, to sum up:  If you have LVDS I/O in a HR bank in a KU, you need to power that bank from 2.5V and use the LVDS_25 IO Standard.   In turn, any single-ended I/O in that bnk also need to be @ 2.5V as well. 

 

Both 1.8V and 3.3V are not valid voltages for the BANK then when using LVDS in a HR bank.  

 

Thanks


Jesse

 

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Xilinx Employee
Xilinx Employee
2,503 Views
Registered: ‎07-23-2015

Re: Question about Kintex Ultrscale HR Bank @ 1.8V, outputting LVDS signals ...

@jechambe-koe  Minor clarifications to your statements


If you have LVDS I/O in a HR bank in a KU, you need to power that bank from 2.5V and use the LVDS_25 IO Standard. 

 


If using LVDS as Outputs, then VCCO needs to be at 2.5V only. If you have LVDS as "only" Inputs in that Bank, you can  have VCCO other than 2.5V provided you follow the caveats that come with it. Check Note 1 under Table 1-77 of UG571 referred by sandrao. 

 


 Both 1.8V and 3.3V are not valid voltages for the BANK then when using LVDS in a HR bank.  

 

 


True if LVDS are Outputs. If "only" Inputs refer to above statement on VCCO. 

 


 In turn, any single-ended I/O in that bnk also need to be @ 2.5V as well.  


Single Ended you are much much restricted by the VCCO of that Bank and so yes. 

 

- Giri
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Teacher muzaffer
Teacher
2,490 Views
Registered: ‎03-31-2012

Re: Question about Kintex Ultrscale HR Bank @ 1.8V, outputting LVDS signals ...

@jechambe-koe this AR is for 7 series https://www.xilinx.com/support/answers/43989.html but it is quite likely to apply to ultrascale too.

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