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aponchak1
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Registered: ‎02-11-2020

RF Analyzer - Access to original projects used to generate the provided bitstreams

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I'm using Vivado 2019.2.1.

I have an UltraScale+ RFSoC (ZU28DR) based board (not a ZCU111 or other Xilinux supplied board) which I'm working to use with the RF Analyzer tool (v1.5).

As an experiment, I simply tried loading one of the bitstreams (RF_Analyzer_28DR_20mA.bit) that came with the RF Analyzer tool. After successfully loading the bitstream and selecting "Select Target", the GUI displayed a red "Error" in the low left corner of each Tile. Upon examination of the Tile Status, I observed that the PLL(s) are not locked, which is understandable because I had not configured the SYSREF and REFCLK of the ADC and DAC.

I want to recreate this bitstream, and then include the necessary circuitry to support programming my boards clock generators.

As a first step, I simply want to recreate the bitstream behavior to match that of the one provided with the RF Analyzer tool, i.e. unlocked PLL. I followed the instructions from https://www.xilinx.com/Attachment/RFAnalyzer_Tutorial.pdf and https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Analyze-That-Unboxing-the-RF-Analyzer-Tool-Part-2/ba-p/987241, but was not successful in replicating the performance of the provided bitstreams.

Would a copy of the original project be provided that produce the RF_Analyzer_28DR_20mA.bit?

Alternatively, could more concise information be provided to aid in the success of recreating the performance of the provide bitstream, like, what is the exact configuration of the RF Data Converter IP that was used to create the Example IP Project?

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vve
Xilinx Employee
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Registered: ‎01-22-2008

I might be a little late to answer this, but hopefully not too late.

The problem might be the version of RF analyzer and version of Vivado not working together correctly. 

I would recommend using Vivado 2020.1 with RF analyzer from this link: 

https://www.xilinx.com/member/forms/download/xef.html?filename=Distribution_RF_Analyzer.zip

If you cannot, then please post a response and I will think of a work around. 

 

Also, coming back on the original post, in the latest version of RF analyzer, you will find the .xci file we used to generate the bitstreams so it is much easier to reproduce it.

Vincent. 

 

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pthakare
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Registered: ‎08-08-2017

Hi @aponchak1 

These bitstreams provide the maximum RF configuration flexibility.

Maximum configuration means DDC/DUC , NCO everything supported in IP is enabled.

You mentioned "but was not successful in replicating the performance of the provided bitstreams." , Can you please elaborate more on this ? What configuration is not working for you.

 

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aponchak1
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Registered: ‎02-11-2020

The configuration of the RF Data Converter IP that I've attempted to build and use for generating the Open IP Example Design...bitstream and test:

  • Basic:
    • ADC Tile 227, only ADC1 is enabled.
      • Configured as Digital Output Data = I/Q, Dec=2x, Samples=8, (so that Require AXI4-Stream clock = 100MHz), Mixer: Fine, Mixer Mode: Real -> I/Q
    • DAC Tile 229, DAC 1 and DAC 3 are enabled.
      • Both configured as DAC, Analog Output Data = Real, Dec=2x, Samples=16, so that Require AXI4-Stream clock = 100MHz, Mixer: Fine, Mixer Mode: I/Q -> Real
  • System Clocking:
    • ADC 227 and DAC 229, sample rate = 1.6 GHz
  • Advanced:
    • RF Analyzer = Enabled
    • AXI4-Lite Clock = 50

I'll try this again with the max maximum configuration...

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aponchak1
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Registered: ‎02-11-2020

I tried maximizing the configuration of the RF DC IP, but it's still not working. When performing "Select Target" in the RF Analyzer, I get an "ERROR: JtagIdcode EXECUTE". I'd would prefer a list or reference design/tcl for replicating exactly what maximizing means versus what I think it means (a little more hand holding would be welcomed). I've attached my project's tcl, so that you know exactly the make up of my project.

For my next attempt...
With your suggestion of maximizing the configuration of the IP as a guiding light, I'm planning to reference what is displayed in the RF Analyzer GUI, when the 'provided' RF_Analyzer_28DR_20mA.bit file is loaded, and configure the IP based on what I am able to ascertain by selecting different ADC/DAC Tiles in the GUI, etc.
IP configuration selection settings that are difficult to determine from the GUI are, and I could use further guidance on:

System Clocking tab:
What is AXI4-Lite Clock set to? (Mine is = 57.5)
Is the PLL checked for all ADCs and DACs? (I checked them all)

Advanced tab:
ADC & and DAC - All boxes that are selectable are checked

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aponchak1
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Registered: ‎02-11-2020

Another failure, same as last time, i.e. when performing "Select Target" in the RF Analyzer, I get an "ERROR: JtagIdcode EXECUTE". Attached is the project tcl file which was created by reviewing the RF Analyzer GUI and its ADC/DAC tile settings, when the 'provided' RF_Analyzer_28DR_20mA.bit file is loaded.

There are more permutations of the RF DC IP, than I have time to try. In comments in the link's that I mentioned in the original post, state "Configure the IP per your board requirement", which I took this to mean I could enable any combination of the ADC and DAC, and that is supported by the RF Analyzer tool. The 'provided' bitstream allows the "Select Target" to succeed and the GUI to display the configuration of the RF DC IP, but not for any of my bitstreams. So what  are the other requirements that are not being met by my project? In both cases, the SYSCLK and REFCLK are not setup, so this should be the problem. Since STARTUPE3 and Microblaze are implemented, then reset and local clocks are defined, so what else is there?

Aside from using a different version of Vivado, I'm at a loss of what to try. Thoughts?

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vve
Xilinx Employee
Xilinx Employee
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Registered: ‎01-22-2008

I might be a little late to answer this, but hopefully not too late.

The problem might be the version of RF analyzer and version of Vivado not working together correctly. 

I would recommend using Vivado 2020.1 with RF analyzer from this link: 

https://www.xilinx.com/member/forms/download/xef.html?filename=Distribution_RF_Analyzer.zip

If you cannot, then please post a response and I will think of a work around. 

 

Also, coming back on the original post, in the latest version of RF analyzer, you will find the .xci file we used to generate the bitstreams so it is much easier to reproduce it.

Vincent. 

 

View solution in original post

aponchak1
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Registered: ‎02-11-2020

Vincent,

Thanks for the response.

As an update to my previous post, I have had some success with building an RF Analyzer bitstream using 2018.3. Specifically, with the inclusion of a SPI circuit for programming the on-board LMX2592 upon power up, the RF Analyzer GUI shows each of the ADC/DAC Tiles  in "Green", and no red colored "ERROR", which was not the case with 2019.2.1, which exhibited JTAG communication failures.

Unfortunately, the 2018.3 bitstream does not seem to have data flowing properly, because none of the DACs output data at the RF connectors, and none of the ADCs show signal activity when sourced from an external signal generator. I've yet to debug via ILA, but that may be my next step, or try 2020.1 as you suggest.

Thanks for providing the latest (v1.6) RF Analyzer, I'll definitely give it a try, with my 2018.3 and 2019.2.1 bitstreams.

Per you suggestion, I explored the included XCI files as well. I attempted to open the RF_Analyzer_28DR_20mA in three versions of Vivado: 2018.3, 2019.2.1 and 2020.1. I found that it was not customizable in 2018.3 or 2020.1, because it looks to have been created using 2019.2.1, which is an order version of RF DC v2.2, not the latest (v2020.1, v2.3). I'd like to explore moving to 2020.1, but am reluctant based on the version issues I experience so far. Could a known-working 2020.1 version of the RF DC IP be provided for exploring creation of the bitstream on my own card?

Adam

 

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aponchak1
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Registered: ‎02-11-2020

Vincent,

I confirmed that by using the latest RF Analyzer v1.6, I am no longer observing JTAG/communications issues for bitstreams built under 2019.2.1.
(I have not tried bitstreams built under 2018.3 or 2020.1.)

Thanks for the assistance and the installer for the updated RF Analyzer,
Adam

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