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geurin
Observer
Observer
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Registered: ‎10-18-2018

RFSOC Data Converter Clock Out Rate

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I have my ADC tile sampling at 4.096Gsps.  Therefore on the System Clocking tab I have the following rates for the ADC clock out for PL use:  256, 128, 64 and 32MHz.

However, when I look at the API function XRFdc_SetFabClkOutDiv(), I have the following configuration choices:

XRFDC_FAB_CLK_DIV1
XRFDC_FAB_CLK_DIV2
XRFDC_FAB_CLK_DIV4
XRFDC_FAB_CLK_DIV8
XRFDC_FAB_CLK_DIV16
 
I'm assuming that the Clock Out selection on the GUI is also setting the output divisor, but I have one more choice in the API vs. the GUI.
 
So the question is, what is the input clock to the divisor??  Does the DIV1 selection correspond to 256MHz on the GUI?  Is DIV16 a legal setting?

 

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klumsde
Moderator
Moderator
907 Views
Registered: ‎04-18-2011

To be more correct there is no divide by 1 allowed on the ADC tile output clock.

You have not missed it. I thought that we used to call it out in the IP product Guide but it seems I don't see it. It is implied in the description in the product guide. 

The clock output here is a divided version of the digital clock inside the tile(sample clock /8)

Options for the ADC are DIV2/4/8/16

For a DAC DIV1/2/4/8/16 is allowed. 

You can see this in the IP:tile_output_clk.JPG

 

A clock out more than 500 on the DAC is stopped here. 

You only have /2 in this case. tile_output_clk500_linit.JPG

 

Acid test is to try yourself to change it at run time using the driver. 

u32 XRFdc_SetFabClkOutDiv(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
u16 FabClkDiv)
{
u32 Status;
u32 BaseAddr;

Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);

Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Tile_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Requested tile not "
"available in %s\r\n", __func__);
goto RETURN_PATH;
}

if ((FabClkDiv != XRFDC_FAB_CLK_DIV1) &&
(FabClkDiv != XRFDC_FAB_CLK_DIV2) &&
(FabClkDiv != XRFDC_FAB_CLK_DIV4) &&
(FabClkDiv != XRFDC_FAB_CLK_DIV8) &&
(FabClkDiv != XRFDC_FAB_CLK_DIV16)) {
metal_log(METAL_LOG_ERROR, "\n Invalid Fabric clock out "
"divider value in %s\r\n", __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}

BaseAddr = XRFDC_DRP_BASE(Type, Tile_Id) + XRFDC_HSCOM_ADDR;

if ((Type == XRFDC_ADC_TILE) &&
(FabClkDiv == XRFDC_FAB_CLK_DIV1)) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid clock divider "
"in %s \r\n", __func__);
goto RETURN_PATH;
} else {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_HSCOM_CLK_DIV_OFFSET,
XRFDC_FAB_CLK_DIV_MASK, FabClkDiv);
}

Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}

Have a look at the section highlighted red. 

If you are aiming this at an ADC and trying to pass it the DIV1 setting, your call will fail and the application will error out with "Invalid Clock Divider"

Keith 

 

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tenzinc
Moderator
Moderator
1,076 Views
Registered: ‎09-18-2014

To me it looks like the IP is missing the divide by 1 option. The input is the fabric clock. At 4.096Gsps with a fabric clock of 512MHz, DIV16 gives you 32 MHz which is valid. I can look into why the IP might be missing DIV1.

 

Regards,

T



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geurin
Observer
Observer
1,029 Views
Registered: ‎10-18-2018

So the IP will output 512MHz with DIV1.  That is excellent news as we had been doing standalone (no software) proof of concept routes and been having to put a PLL in there to double the rate to 512.  Thanks!

Curious to know if the lack of 512 on the GUI is just an oversight.

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klumsde
Moderator
Moderator
968 Views
Registered: ‎04-18-2011

Hi @geurin

The maximum frequency of the ADC and DAC tile output clock cannot exceed 500mhz so div1 is not an option in this case..

Keith

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geurin
Observer
Observer
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Registered: ‎10-18-2018

I looked through the datasheet and didn't see that number documented anywhere.  Did I miss it?

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klumsde
Moderator
Moderator
908 Views
Registered: ‎04-18-2011

To be more correct there is no divide by 1 allowed on the ADC tile output clock.

You have not missed it. I thought that we used to call it out in the IP product Guide but it seems I don't see it. It is implied in the description in the product guide. 

The clock output here is a divided version of the digital clock inside the tile(sample clock /8)

Options for the ADC are DIV2/4/8/16

For a DAC DIV1/2/4/8/16 is allowed. 

You can see this in the IP:tile_output_clk.JPG

 

A clock out more than 500 on the DAC is stopped here. 

You only have /2 in this case. tile_output_clk500_linit.JPG

 

Acid test is to try yourself to change it at run time using the driver. 

u32 XRFdc_SetFabClkOutDiv(XRFdc *InstancePtr, u32 Type, u32 Tile_Id,
u16 FabClkDiv)
{
u32 Status;
u32 BaseAddr;

Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XRFDC_COMPONENT_IS_READY);

Status = XRFdc_CheckTileEnabled(InstancePtr, Type, Tile_Id);
if (Status != XRFDC_SUCCESS) {
metal_log(METAL_LOG_ERROR, "\n Requested tile not "
"available in %s\r\n", __func__);
goto RETURN_PATH;
}

if ((FabClkDiv != XRFDC_FAB_CLK_DIV1) &&
(FabClkDiv != XRFDC_FAB_CLK_DIV2) &&
(FabClkDiv != XRFDC_FAB_CLK_DIV4) &&
(FabClkDiv != XRFDC_FAB_CLK_DIV8) &&
(FabClkDiv != XRFDC_FAB_CLK_DIV16)) {
metal_log(METAL_LOG_ERROR, "\n Invalid Fabric clock out "
"divider value in %s\r\n", __func__);
Status = XRFDC_FAILURE;
goto RETURN_PATH;
}

BaseAddr = XRFDC_DRP_BASE(Type, Tile_Id) + XRFDC_HSCOM_ADDR;

if ((Type == XRFDC_ADC_TILE) &&
(FabClkDiv == XRFDC_FAB_CLK_DIV1)) {
Status = XRFDC_FAILURE;
metal_log(METAL_LOG_ERROR, "\n Invalid clock divider "
"in %s \r\n", __func__);
goto RETURN_PATH;
} else {
XRFdc_ClrSetReg(InstancePtr, BaseAddr, XRFDC_HSCOM_CLK_DIV_OFFSET,
XRFDC_FAB_CLK_DIV_MASK, FabClkDiv);
}

Status = XRFDC_SUCCESS;
RETURN_PATH:
return Status;
}

Have a look at the section highlighted red. 

If you are aiming this at an ADC and trying to pass it the DIV1 setting, your call will fail and the application will error out with "Invalid Clock Divider"

Keith 

 

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

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geurin
Observer
Observer
891 Views
Registered: ‎10-18-2018

Perfect. Thanks for the detailed reply!

 

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klumsde
Moderator
Moderator
885 Views
Registered: ‎04-18-2011

In fact, if we want to be really complete we should add a check on the fs of the DAC tile. From just looking at the source code you could ask for an invalid setting on the DAC clock output when you have an fs>4GSPS for your DAC 

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