12-20-2019 03:49 AM
We need to decide whether to use Gen1 or Gen3 RFSOCs for a product.
Our main selection criterion is the broadband ADC noise. We would like to have a close look at it than just doing some math on the NSD number in the data sheet.
Is it possible to get a larger sample (128k samples or more) of ADC noise data for these chips? Maybe someone with an evaluation board could connect the input to GND and creat sample data for us?
That would be very helpful.
12-20-2019 04:58 AM
12-20-2019 01:34 PM
Does this mean that the NSD is entirely flat over the full frequency range?
I would suppose that there is at least some frequency dependancy in the noise that is not represented by the NSD figure.
Also, there are no Gen3 boards availabe that I am aware of so I was hoping that someone inside Xilinx could provide that data.
4096 Msps for both chips and 5Gsps for Gen3 would be the ideal dataset for us, but we could probably learn a lot from different sampling rates as well.
12-21-2019 03:44 AM
01-02-2020 11:23 PM
Here is my two cents,
If you are looking for the detail NSD testing result in full bandwidth. you can please reqeust to access this website and download the char report of Gen1 device.
01-03-2020 01:03 AM
However, if I understand the NSD plot in that document correctly, it shows the full bandwidth NSD plotted against the frequency of a -1dB sine wave fed into the ADC.
What I am looking for is the spectrum of the noise with no input (or a fixed frequency input). Or the same data in the time domain.
01-03-2020 02:20 PM
Not providing the ADC with an input is going to have implications for the background calibration. This needs energy to converge. What is the real purpose of this test? It is not clear to me.
01-04-2020 12:03 AM
We need to detect pulses on the input. Our key performance characteristic is the ration between full scale and the smallest pulse that we can detect.
If the noise is perfectly white this ratio is given by the SNR measured either with a low frequency input or low amplitude input or computed using the noise histogramm (we don't care about distortion for this metric).
The characterisation report therefore contained the information that low frequency inputs improve the noise by about 1dB, which is good to know.
However, for non-white noise we can do better or worse than the SNR, depending on the shape of the noise. I need information on the noise shape as a spectrum or a set of noise samples to compute the dynamic range that we can achieve.
e2v and ADI simply sent us sample data when we asked for that. TI needed us to jump through some bureaucracy loops and our Xilinx FAE did nothing for a couple of months but now wants to lend us a Gen1 evaluation board for measurements.
01-04-2020 10:28 AM
01-06-2020 07:02 AM
I think it makes sense to try it out for yourself. I find the approach is a little unorthodox. I guess the idea of taking the noise profile and trying to extrapolate the SNR is not what I am used to.
I think you should think about where SNR really comes from.
It is a combination of the ADC quantization, thermal noise(the Capacitive elements of the ADC for example) then the clock jitter.
As you have seen backing off the input or looking at lower frequency CW improve SNR. This is directly because you are less impacted by the clock uncertainty at the sampling instant.
01-06-2020 09:36 AM
that is exactly why I need noise data to do calculations myself:
The equations you are quoting are valid only for sine waves. For our problem the effects of quantisation noise and jitter are zero. We are only concerned with noise sources that exist for DC inputs.
Beside thermal noise and flicker noise there might noise from other parts of the system coupled by power supply or EMI.
There are provable optimal filters for detecting small pulses in noise. If the noise is white I can derive the dynmic range in closed form. If not I need a histogramm of the filtered noise to compute it.