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Visitor puskasdj
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2,268 Views
Registered: ‎10-18-2018

RFSoC ADC Real-to-IQ Not Working as Expected

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Hello,

I have a custom board with a xczu27dr RFSoC (ES1), and I'm having trouble getting Real-To-I/Q mode working properly. It seems the quadrature (Q) axi4-stream is stuck at zero (or near zero), while the in-phase (I) stream appears to be working normally. I get "some" output on the Q stream (very low magnitude) if I input a very powerful signal into the ADC. When I process the data (e.g., in MATLAB) I see the correct signal in the Q data (matches my input frequency), but it's not nearly as sensitive as the I data stream. See the attached waveforms.

I'm sampling at 2 Gsps with a 250 MHz reference clock to the PLL. No input signal is required to observe this behavior; sampling only noise is sufficient.

I've tried Vivado 2018.2, 2018.2.1 and 2018.3 all with no difference. This is a PL-only design, so I don't yet have a PS running in which I can send RFDC API commands.

Other things I've tried (all with no appreciable difference):

Changing the NCO phase and/or frequency, using coarse and/or fine mixer modes, using the "fast NCO reset" from the PL (using 2018.3).

One interesting observation is I can swap the "good" data onto the Q stream (leaving the I stream at low magnitude) if I use a 90 degree NCO phase offset. It's as if one half of the NCO is internally powered down. The red/green ILA plot shows this behavior; in this case ch5 is configured with a 90 deg phase offset and ch0 is 0 deg.

I've read that "resetting the NCO phase" with the API is required after startup "to put the mixer in a valid state", but I'm using a single ADC (no multi-tile sync), so is this still relevant?

I've also read that some calibration steps require an input signal above a specific threshold (-40 dBFS)? Could this be a factor?

Any help is appreciated. Thanks, Dan

2018.3_same_problem.PNGch0_zoomout.pngch0_and_ch5_ila.PNG

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Community Manager
Community Manager
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Registered: ‎08-30-2011

Re: RFSoC ADC Real-to-IQ Not Working as Expected

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Hello @puskasdj

I think that's the reason. Both I and Q are shifted to DC so that you can only see I and Q is Zero. Fs/2 is the same.

Please check if a non zero  arbitrary frequency shift between -fs/2 and fs/2.

Thanks,

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Moderator
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Registered: ‎04-18-2011

Re: RFSoC ADC Real-to-IQ Not Working as Expected

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Hi the phase of the NCO must be reset at the beginning. Please try this step. A simple bare metal application can be used.

 

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Moderator
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Re: RFSoC ADC Real-to-IQ Not Working as Expected

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Also can you tell me what happens when you use the coarse mixer.
this does not use the NCO.
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Visitor puskasdj
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Registered: ‎10-18-2018

Re: RFSoC ADC Real-to-IQ Not Working as Expected

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I get the same result using the coarse mixer. See attached. In these captures ch4 was setup to use the coarse mixer while ch5 was setup to use the NCO, each with the same frequency shift (1 GHz).

I'll try resetting the NCO from the PS today. But when I tried to reset it from the PL fabric last week (in 2018.3) it did not have an effect (unless I have a bug, I'll check that today too). But are these equivalent? i.e., what's the difference resetting the NCO phase from the PL vs. the PS?

ch4_and_ch5_ila.PNGch4_and_ch5_settings_.png

Thanks, Dan

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Registered: ‎04-18-2011

Re: RFSoC ADC Real-to-IQ Not Working as Expected

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Hi Dan, 

I have been re-reading your post. So you are not putting in any signal. 

Can you show me what this is like with a known input. 

We have the RF Analyser tool. It might make sense to try it in your set up. 

 

https://www.xilinx.com/products/silicon-devices/soc/rfsoc.html#toolsExamples

 

Keith 

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Visitor puskasdj
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Registered: ‎10-18-2018

Re: RFSoC ADC Real-to-IQ Not Working as Expected

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Hi Keith,

Thanks for your reply.

The result is the same (or similar) with a non-trivial input signal, such as a sinusoid. I have noticed the data on the Q channel fluctuates slightly when inputting a very strong signal...in this case, the data is correct (i.e., I observe the proper signal in post-processing), but significantly reduced in magnitude compared to the I channel. I/Q should have equal power coming out of the mixer(s). The I channel always looks correct, with strong output power unless I change the NCO phase. When I change the NCO phase the output magnitude varies between the I and Q channels how I would expect, but with no new information present. I and Q should double the amount of information available for processing (they are orthogonal).

I verified I was resetting the NCO phase correctly from within the PL, but the problem remains. I want to try this using the PS API as well, but I don't have a metal project handy. I'll look into this more.

I'm beginning to suspect the self-calibration as a factor. The new documentation (v2.1 of PG269) has a lengthy section on calibration and it's quite complex, requiring input signals within a specific range of magnitudes. I'm not sure this is going to be viable for our application (we can't guarantee precise control of the input signal at every power-on). But it would be good to know if this is the cause. I have noticed qualitatively that the Q channel begins to "warm up" after running for a bit (or after inputting a signal?); I don't have hard data to back me up, but at power-on the Q channel is flat zeros, and later it fluctuates at low power.

Another question I have is related to the production vs. engineering silicon. We're using an ES1 part for these tests. I have access to a production part as well, and I'd like to try that out soon.

Any other ideas on this is welcome.

Thanks, Dan

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Moderator
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Registered: ‎04-18-2011

Re: RFSoC ADC Real-to-IQ Not Working as Expected

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Hi @puskasdj

I don't really think this is to do with calibration, the mixer is in the data path which comes after the ADC output. 

So Foreground calibration really just requires you to have no signal energy present over the Offset Spur locations. After the start up the ADC Gain and time interleaving spurs require signal energy to converge. 

For this, you need to tell the core which nyquist zone the signal is in and then where in the nyquist zone it is. (Calmode 1 or Calmode2)

Weak input power less than -40dBFS can cause it not to converge.

It is worth trying with a proper input tone with the nyquist zone and the calmode properly set. Then a phase reset to the tile. 

Keith 

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Visitor puskasdj
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Registered: ‎10-18-2018

Re: RFSoC ADC Real-to-IQ Not Working as Expected

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Hi Keith,

I've tried with and without an input signal, with and without resetting the NCO. In all cases I get the same result.

Thanks, Dan

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Community Manager
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Registered: ‎08-30-2011

Re: RFSoC ADC Real-to-IQ Not Working as Expected

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@puskasdj

I noticed that you set the sample rate = 2Gsps and the NCO frequency = 1Ghz.

How about set NCO frequency to other value between -fs/2 to fs/2 (not include fs/2?) some value like 0.456Ghz?

 

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Visitor puskasdj
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Registered: ‎10-18-2018

Re: RFSoC ADC Real-to-IQ Not Working as Expected

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Hi @zhendon,

Those were older settings I was using to try out some different things. Typically I'm testing with mixer settings of 0 GHz shift and 0 phase offset.

But that's another question -- will a zero-frequency shift (partially) disable or affect the mixer?

I'll try again with an arbitrary mixer frequency setting.

Thanks, Dan

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Re: RFSoC ADC Real-to-IQ Not Working as Expected

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Hello @puskasdj

I think that's the reason. Both I and Q are shifted to DC so that you can only see I and Q is Zero. Fs/2 is the same.

Please check if a non zero  arbitrary frequency shift between -fs/2 and fs/2.

Thanks,

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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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Visitor puskasdj
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Registered: ‎10-18-2018

Re: RFSoC ADC Real-to-IQ Not Working as Expected

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Hi @zhendon,

I think you're right. I had experimented with some other NCO values previously, but abandoned that after seeing some unexpected results. But also at that time I didn't know about the NCO reset. I think I now have a better understanding of how this is supposed to work.

One problem I'm facing is that our RF card was designed without the RFSoC capabilities in mind (DDC/DUC etc). So, our signal is already at baseband when it enters the board, which implies a zero frequency shift. I'll have to work around this.

I'm going to try as you suggested, setting the NCO frequency to something arbitrary.

But...do you know what limitations there are on this setting? I believe the tool allows "any frequency" shift between +/-10 GHz, but you're suggesting I stay within +/- Fs/2. How far can I push this? And are there other specific frequencies that aren't viable? E.g., k*Fs/2 for integer k or something?

Thanks to you and @klumsde for shedding some light on this for me -Dan

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Visitor puskasdj
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Registered: ‎10-18-2018

Re: RFSoC ADC Real-to-IQ Not Working as Expected

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Hi @zhendon @klumsde,

Any update here? What are the limits of the NCO?

PG269 suggests two (different) limits for NCO frequency: on p23 for the PL-based NCO reset there is a 48-bit number which has an advertised range +/-Fs/2. Later on p171, when discussing the API, the 48-bit number has a range of +/-Fs? Are these functions different in any way?

In addition, the IP allows the user to enter any value between +/-10GHz. So which is it? Some clear(er) guidance here would be helpful.

nco_limits_1.PNGnco_limits_2.PNG

Thanks, Dan

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Registered: ‎04-18-2011

Re: RFSoC ADC Real-to-IQ Not Working as Expected

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The mixer setting is - fs/2 to fs/2

In this case entering a value between - 10ghz and 10ghz is just a convenience of the IP. Ultimately this will be mapped to a value in the - fs/2 to +fs/2 range

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Observer tki
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Registered: ‎08-20-2018

Re: RFSoC ADC Real-to-IQ Not Working as Expected

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Hi zhendon,

Coming back to this
So what was the actual solution here ?

-Only to use arbitary frequency shift that is different than fs/2 ?

-is there anything else needed ?

 

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Community Manager
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Registered: ‎08-30-2011

Re: RFSoC ADC Real-to-IQ Not Working as Expected

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Hi Tki,

Although IP allows you to input NCO frequency between +/-10Ghz. But in most case, the customer are setting the NCO frequency natually between in +/-Fs/2.

The original issue for this issue is NCO frequency set to DC (0 Hz and Fs/2 can be considered both DC) so we can see only I at the data interface side. So if the NCO frequency can be set different to 0 Hz or Fs/2, then both I and Q can be seen at data interface.

 

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