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Voyager
Voyager
874 Views
Registered: ‎02-17-2009

RFSoC ADC linearity issue

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Hello,

We've been running ADC linearity tests on a ZU28DR device (basically just applying a CW, changing its level in 1 dB steps and measuring the digital amplitude at each step) and found that there was a strange step at about -16 dBFS. We saw this happening on two devices however in one case the step was 0.42 dB instead of the expected 1 dB and in another case it was 1.6 dB instead of 1 dB. 

We are also finding that the ADC overflows when the output digital signal is at about -6 dBFS.

Here is our ADC configuration:

Screenshot - 13-Jul-2020 , 5_00_43 PM.png

The ADC sampling clock is set to 3 GHz.

 

Thanks,
/Mikhail

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Voyager
Voyager
600 Views
Registered: ‎02-17-2009

Hi @klumsde ,

I am very embarrassed to admit that the problem was with our signal generator. In other words, there is no issue with the RFSoC ADC linearity. Thank you for your help.

/Mikhail

 

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Moderator
Moderator
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Registered: ‎04-18-2011

I would be interested in repeating this test in RF analyzer. 

Can you plot the result there and share it here?

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Voyager
Voyager
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Registered: ‎02-17-2009

Hi @klumsde ,

This was done with our own h/w design on a 3rd party board and our own software. I have never tried the RF analyzer. I need to see what's involved in using it.

Thanks,
/Mikhail

 

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Moderator
Moderator
844 Views
Registered: ‎04-18-2011

It can work on any device / any board

There is documentation in PG269

Also these blogs give a step by step example

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Analyze-This-Unboxing-the-RF-Analyzer-Tool-Part-One/ba-p/964731

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Analyze-That-Unboxing-the-RF-Analyzer-Tool-Part-2/ba-p/987241

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Voyager
Voyager
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Registered: ‎02-17-2009

Hi @klumsde,

One complication is that I need to have a PCI subsystem on the PL side as a part of the design to be able to program our clock synthesizer using existing software... 

Thanks,
/Mikhail

 

 

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Voyager
Voyager
734 Views
Registered: ‎02-17-2009

@klumsde wrote:

I would be interested in repeating this test in RF analyzer. 

Can you plot the result there and share it here?


Hi @klumsde ,

I have got the RF analyzer running on our board and the linearity problem didn't go away. However, I can't see how I can generate a linearity plot from this tool if that what you meant... So, here are some tabulated results and a capture example:

Signal Power from a signal generator, dBmSignal Power in RF Analyzer, dBFSMeasured Step, dB
+2-10.83 
+1-11.831.0
0-12.841.01
-1-14.291.45
-2-15.280.99
-3-16.281.0

 

Screenshot - 17-Jul-2020 , 3_16_41 PM.png

We have verified that it's not a signal generator problem.

Thanks,
/Mikhail

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Moderator
Moderator
650 Views
Registered: ‎04-18-2011

Is the sample frequency 3Ghz?

I see that the set up is Real to IQ mode. 

Where is the CW? Does it change if the location of the CW is moved or does making it real to real mode and bypassing the mixer make a difference. 

my suspicion here is some impact from the interleaving calibration or perhaps it is coming from the ADC dither. 

Can you try with Dither off? 

Can we try to bypass the mixer?

 

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Voyager
Voyager
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Registered: ‎02-17-2009

Hi @klumsde ,

I am very embarrassed to admit that the problem was with our signal generator. In other words, there is no issue with the RFSoC ADC linearity. Thank you for your help.

/Mikhail

 

View solution in original post

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Moderator
Moderator
576 Views
Registered: ‎04-18-2011

No problem, I'm glad you tracked it down

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