RFSoC ADC linearity issue

[mmatusov]

Hello,

We've been running ADC linearity tests on a ZU28DR device (basically just applying a CW, changing its level in 1 dB steps and measuring the digital amplitude at each step) and found that there was a strange step at about -16 dBFS. We saw this happening on two devices however in one case the step was 0.42 dB instead of the expected 1 dB and in another case it was 1.6 dB instead of 1 dB. 

We are also finding that the ADC overflows when the output digital signal is at about -6 dBFS.

Here is our ADC configuration:

The ADC sampling clock is set to 3 GHz.

Thanks,
/Mikhail

[klumsde]

I would be interested in repeating this test in RF analyzer. 

Can you plot the result there and share it here?

[mmatusov]

Hi @klumsde ,

This was done with our own h/w design on a 3rd party board and our own software. I have never tried the RF analyzer. I need to see what's involved in using it.

Thanks,
/Mikhail

[klumsde]

It can work on any device / any board

There is documentation in PG269

Also these blogs give a step by step example

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Analyze-This-Unboxing-the-RF-Analyzer-Tool-Part-One/ba-p/964731

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Analyze-That-Unboxing-the-RF-Analyzer-Tool-Part-2/ba-p/987241

[mmatusov]

Hi @klumsde,

One complication is that I need to have a PCI subsystem on the PL side as a part of the design to be able to program our clock synthesizer using existing software... 

Thanks,
/Mikhail

[mmatusov]

---

@klumsde wrote:

I would be interested in repeating this test in RF analyzer. 

Can you plot the result there and share it here?

---

Hi @klumsde ,

I have got the RF analyzer running on our board and the linearity problem didn't go away. However, I can't see how I can generate a linearity plot from this tool if that what you meant... So, here are some tabulated results and a capture example:

Signal Power from a signal generator, dBm	Signal Power in RF Analyzer, dBFS	Measured Step, dB
+2	-10.83
+1	-11.83	1.0
0	-12.84	1.01
-1	-14.29	1.45
-2	-15.28	0.99
-3	-16.28	1.0

We have verified that it's not a signal generator problem.

Thanks,
/Mikhail

[klumsde]

Is the sample frequency 3Ghz?

I see that the set up is Real to IQ mode. 

Where is the CW? Does it change if the location of the CW is moved or does making it real to real mode and bypassing the mixer make a difference. 

my suspicion here is some impact from the interleaving calibration or perhaps it is coming from the ADC dither. 

Can you try with Dither off? 

Can we try to bypass the mixer?

[mmatusov · Accepted solution]

Hi @klumsde ,

I am very embarrassed to admit that the problem was with our signal generator. In other words, there is no issue with the RFSoC ADC linearity. Thank you for your help.

/Mikhail

[klumsde]

No problem, I'm glad you tracked it down