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viduneth
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Registered: ‎02-26-2020

RFSoC ADC output

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Hello:

I am trying to test the ADCs of the HiTech HTG-ZRF8-R2 board (featuring the ZU28DR chip). I am using the Vivado 2019.2 tool setup and I am seeing ADC output format to be different from what the datasheet states.
Data Converter IP settings (Xilinx Data Converter [XDCIP]  IP 2.2 ) are: 
Sampling rate: 4.096 GSps
Decimation mode: 8x
Samples per AXI4-Stream clock edge: 2 (corresponds to a clock =256 MHz)
Mixer mode: real -> real 
Nyquist zone: 1
Calibration mode: 2

According to the XDCIP the stream words (2 words per clock in my case with 32 bits) consists of 2-bytes which contains of ADC data 12-bits left-shifted by 4. But when I use an ILA to capture the samples (both [31:16]  and [15:0] separately), I see that all 16 bits change. In other words, I am expecting to see the 4 most LSBs to be zeros but I am seeing them carrying some data. Could anyone please let me know if I am missing something here or if this is the expected behavior?

Thank you,
Viduneth

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patocarr
Teacher
Teacher
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Registered: ‎01-28-2008

Hi @viduneth 

  I think you're assuming the padded bits will be zero when that may not be the case. Just take the MSB as defined and ignore the padding LSBs.

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

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patocarr
Teacher
Teacher
898 Views
Registered: ‎01-28-2008

Hi @viduneth 

  I think you're assuming the padded bits will be zero when that may not be the case. Just take the MSB as defined and ignore the padding LSBs.

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

View solution in original post

pthakare
Moderator
Moderator
820 Views
Registered: ‎08-08-2017

Hi @viduneth 

This is expected ,

Bits [3:2] will toggle due to interleaving calibration and dithering 

We can ignore this as ADC is 12 bit accurate.

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viduneth
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Registered: ‎02-26-2020

Thank you for confirming this @pthakare @patocarr...

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chaooxford
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Participant
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Registered: ‎05-16-2018

Hi viduneth,

do you have any example design with ADCs running? like an vivado and sdk project or so?

Best regards,

Chao

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viduneth
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Registered: ‎02-26-2020

Hi Chao,

Sorry for the very late reply as I hadn't noticed your post. 

Do you still need this?

 

Regards,

Viduneth

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chaooxford
Participant
Participant
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Registered: ‎05-16-2018

Hi Viduneth,

Thanks very much for your reply. I still need this. I have sent you an private message in xilinx account with my contact details. 

Best 

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