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gd8021
Participant
Participant
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Registered: ‎09-20-2010

RFSoC DAC

Questions about CLK_DACx (x = location of the DAC):

#1

according to the example design simulation to the DAC, for instance DAC0 more specifically here:

1) it sets the DAC tile register 0x4008 and 0x4004 bit[0] to '1'

2) write data samples and then set Reg 0x4008 to 0x00000108" and Reg 0x4004 bit[1] to '1' again 

3) write Reg 0x200001100, 0x200001200 and 0x200001300 with zeros following by setting 0x4008 bit[3:0] to x"6" and 0x4004 bit[1] to '1' once again 

the CLK_DAC0 is showing up after these. 

 

#2 my questions:

Q1: according to the datasheet, the power-on sequence is done automatically once power applied without any user intervention, right? Which means that CLK_DAC0 shall be ready after sometime of power-on, right?

Q2: was writing Reg 0x200001100, 0x200001200 and 0x200001300 required for CLK_DAC0 output? 

Q2: what 0x200001100, 0x200001200 and 0x200001300 are doing here? 

Q3: should CLK_DAC0 be ready after power-on sequence done? 

Q4: did DAC0_DONE signal indicate the power-on sequence done? 

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gd8021
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Participant
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Registered: ‎09-20-2010

Can anyone from Xilinx answer the questions ASAP? 

Just want to know the minimum configuration or programming or settings for getting CLK_DAC0 out!!!

This programming sequence should be stated in the datasheet. Thanks. 

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