Questions about CLK_DACx (x = location of the DAC):
according to the example design simulation to the DAC, for instance DAC0 more specifically here:
1) it sets the DAC tile register 0x4008 and 0x4004 bit to '1'
2) write data samples and then set Reg 0x4008 to 0x00000108" and Reg 0x4004 bit to '1' again
3) write Reg 0x200001100, 0x200001200 and 0x200001300 with zeros following by setting 0x4008 bit[3:0] to x"6" and 0x4004 bit to '1' once again
the CLK_DAC0 is showing up after these.
#2 my questions:
Q1: according to the datasheet, the power-on sequence is done automatically once power applied without any user intervention, right? Which means that CLK_DAC0 shall be ready after sometime of power-on, right?
Q2: was writing Reg 0x200001100, 0x200001200 and 0x200001300 required for CLK_DAC0 output?
Q2: what 0x200001100, 0x200001200 and 0x200001300 are doing here?
Q3: should CLK_DAC0 be ready after power-on sequence done?
Q4: did DAC0_DONE signal indicate the power-on sequence done?