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Visitor bwtbirchp
Visitor
402 Views
Registered: ‎07-03-2019

RFSoC Detailed Register Map for RF-ADC and RF-DAC Tiles

Hi,

I'm trying to extend the basic demo project for the RFSoC to include two ADCs (on the same tile) and two DACs (again on the same tile). I've successfully managed to get a single ADC-DAC pair working, but when I bring up the second pair I'm seeing what looks to be a high frequency carrier signal injected over the top of my sinewave (see below, the purple signal is the correct output, pink is the one corrupted by high frequency, and the yellow/red diagram shows the two signals overlaid).

2019-07-17_17-11.png

I'm assuming that I've got something wrong in the AXI configuration of the ADC. I'm using the `demo_tb_axi4l_nano_seq.v` and I've added task calls for `call_adc_setup_ip` and `call_adc_disable_mix` for tile 0 slices 0 & 1 - which at least made the two ADCs jump into life.

The problem is that I cannot decode what operations `call_adc_setup_ip` is performing, it's writing to addresses within the 'reserved' range according to PG269, so I can't tell if something bad is being written:

2019-07-17_17-18.png

2019-07-17_17-20_1.png2019-07-17_17-20.png

I don't have the luxury of being able to use the Xilinx driver as I'm running a pure Verilog bench here. 

Does anyone have the full register map available? Or does anyone know if there is some form of aliasing within the register map that explains why I can see writes going to this 'reserved' region?

Thanks,

Peter

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6 Replies
Visitor bwtbirchp
Visitor
343 Views
Registered: ‎07-03-2019

Re: RFSoC Detailed Register Map for RF-ADC and RF-DAC Tiles

Could someone from Xilinx possibly shed any light on this? Thanks!
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Community Manager
Community Manager
336 Views
Registered: ‎08-30-2011

Re: RFSoC Detailed Register Map for RF-ADC and RF-DAC Tiles

Hello Peter,

Sorry for the delayed reply.

The RF products are designed with driver and so there is less information we can access to the full register map. I am also not sure why the simulation is accessing the reserved register area. But I am considering to have your issue reproduced at my side then I can look into it and may get some resource to explain your issue.

May I get your xci then I can know exactly your IP settings, also other necessary modifications to the example design or the simulation file so that I can use these files to reproduce your issue?

thanks,

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Visitor bwtbirchp
Visitor
324 Views
Registered: ‎07-03-2019

Re: RFSoC Detailed Register Map for RF-ADC and RF-DAC Tiles

Hi, 

Thanks for your response. It's probably easiest just for me to send you the entire project, as it's very small. Please find it attached to this message.

Thanks,

Peter

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Moderator
Moderator
309 Views
Registered: ‎04-18-2011

Re: RFSoC Detailed Register Map for RF-ADC and RF-DAC Tiles

The example design test bench does some writes at the start to try to speed up the simulation. 

It will turn off things like chopping in the ADC since this is not material to a simulation such as this... 

@zhendon will try this out and we can check it out. I suspect this is an issue with the mixer settings. Let us know the version of the tools you used? 

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Visitor bwtbirchp
Visitor
298 Views
Registered: ‎07-03-2019

Re: RFSoC Detailed Register Map for RF-ADC and RF-DAC Tiles

@klumsde @zhendon We've been using Vivado 2018.2 for all of our work so far.

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Moderator
Moderator
266 Views
Registered: ‎04-18-2011

Re: RFSoC Detailed Register Map for RF-ADC and RF-DAC Tiles

Hi, 

I think we only started to support tone checking in 2018.3 up until then we turned off the mixer because the stimulus was a ramp

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