07-17-2019 09:25 AM - edited 07-23-2019 01:51 AM
I'm trying to extend the basic demo project for the RFSoC to include two ADCs (on the same tile) and two DACs (again on the same tile). I've successfully managed to get a single ADC-DAC pair working, but when I bring up the second pair I'm seeing what looks to be a high frequency carrier signal injected over the top of my sinewave (see below, the purple signal is the correct output, pink is the one corrupted by high frequency, and the yellow/red diagram shows the two signals overlaid).
I'm assuming that I've got something wrong in the AXI configuration of the ADC. I'm using the `demo_tb_axi4l_nano_seq.v` and I've added task calls for `call_adc_setup_ip` and `call_adc_disable_mix` for tile 0 slices 0 & 1 - which at least made the two ADCs jump into life.
The problem is that I cannot decode what operations `call_adc_setup_ip` is performing, it's writing to addresses within the 'reserved' range according to PG269, so I can't tell if something bad is being written:
I don't have the luxury of being able to use the Xilinx driver as I'm running a pure Verilog bench here.
Does anyone have the full register map available? Or does anyone know if there is some form of aliasing within the register map that explains why I can see writes going to this 'reserved' region?
07-23-2019 03:00 AM
Sorry for the delayed reply.
The RF products are designed with driver and so there is less information we can access to the full register map. I am also not sure why the simulation is accessing the reserved register area. But I am considering to have your issue reproduced at my side then I can look into it and may get some resource to explain your issue.
May I get your xci then I can know exactly your IP settings, also other necessary modifications to the example design or the simulation file so that I can use these files to reproduce your issue?
07-23-2019 04:52 AM
07-24-2019 11:36 AM - edited 07-24-2019 11:41 AM
The example design test bench does some writes at the start to try to speed up the simulation.
It will turn off things like chopping in the ADC since this is not material to a simulation such as this...
@zhendon will try this out and we can check it out. I suspect this is an issue with the mixer settings. Let us know the version of the tools you used?
07-27-2019 05:13 AM
I think we only started to support tone checking in 2018.3 up until then we turned off the mixer because the stimulus was a ramp