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Participant dlee32
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1,664 Views
Registered: ‎05-30-2018

RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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Hello,

I have a question regarding the reference clock frequencies that are selectable by the Vivado RFSoC IP block for the ZCU111

DropDownMenu.png

From the above diagram: It seems that for every sample rate specified the list of selectable reference clocks will differ. It seems like this list is some integer division of the sampling rate. Under certain conditions, there will be a warning message about significant phase noise impacts if the reference clock is selected to be something that is too low. I believe this is in-line with the documentation which states that optimal values for reference clocks should be above 250 MHz.

 

  1. How is this list of reference clocks derived? Is there a formula that can fully derive the selectable range of values? It looks like this list is dynamically created depending on the chosen sampling frequency
  2. I noticed that in one scenario, I set the reference clock to 250 MHz in the IP block in Vivado, however, the RFTool Linux application by default sets it to 245.76 MHz at the Petalinux bootup. This mismatch in reference frequency causes an NCO tone I transmit over the DAC to look very disjointed when looped back into the ADC. Changing it to 250 MHz using the DynamicPLLConfig command fixes it and the tone looks much cleaner. My main question is: Does the RFSoC IP setting for reference frequency also match Reference Clock software settings applied by RFTool or XRFDC API calls?

 

 

 

 

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Moderator
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Registered: ‎04-18-2011

Re: RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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Also, in the SW driver the XRFdc_DynamicPLLConfig takes in the FS and in reference clock you give it and then calls XRFdc_SetPLLConfig to set up the PLL 

 

In here you will see that it Checks R

Next it sweeps the valid values for FBDiv, multiplies by the REFCLK frequency to get a FVCO that is in spec, once it does that it sweeps the output divider to find a PLL output that best matches your requested FS. 

So the short answer is that it won't allow you to pick an FVCO that is not in the 8.5Ghz and 12.8Ghz range. 

I hope that this clears it up. 

 

Keith 

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Moderator
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Re: RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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Hi @dlee32

In this case the ZCU111 has some RF PLLs for clock generation and the ADC or DAC tile also has an internal PLL to do frequency synthesis of the sample clock from an incoming reference clock on the board. 

The images you share show how to configure the PLL in the IP, we ask you for the sample clock you need, then give you a set of valid input clock frequencies to give you this sample clock and under the hood we program the PLL settings. This is not the same as programming the LMK/LMX on the board. 

The structure of the tile PLL is like this:tile_pll_diagram.JPG

 

the output frequency is given by 

Fs = (Fin/R)*(FBDiv/M)

in 2018.3 we've added a summary tab to show you the settings once you've selected the input clock. 

So if you pick 250Mhz from the drop down, this gives you a certain set of PLL settings. if you come along after and input a different clock from the RF PLL on the board then obviously there is going to be an issue with the sample clock. 

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Adventurer
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Registered: ‎11-14-2008

Re: RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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What are the integer ranges of R, M, and FBdiv?

 

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Moderator
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Re: RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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We don't publish the ranges for these. 

In this case the supported flow is to set the sample rate and pick a valid input clock to the tile PLL from the list of valid options. 

Keith 

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Adventurer
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Registered: ‎11-14-2008

Re: RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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Essentially, use the RFDC Vivado IP wizard as the decoder ring. Got it.

Thanks Keith!

(tried to give you kudos, but the icon is not responding)

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Moderator
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Registered: ‎04-18-2011

Re: RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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No Problem, 

the main thing to be aware of is that the reference divider should be 1, you've seen it warn you in the tools I think, and the input should be >245Mhz to get the best phase noise performance out of it. 

 

Keith 

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Adventurer
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Registered: ‎11-14-2008

Re: RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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Makes sense. I think this is a VCO fact of life. Best phase noise is achieved with the largest input frequencies.

Also, dlee32 pointed me to PG269, pg 96, where it lists the values used by the API. Probably not the limits of the hardware, but these at least give us a sandbox to play in.

Thanks again!

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Participant dlee32
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Registered: ‎05-30-2018

Re: RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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Hi Keith, a follow-up question on the appropriate reference clock settings.

As Matt pointed out, UG269 points out the different ranges of all the reference divider ( 1 to 4 ), feedback divisor (13 to 160) and Output divisor (2 to 64). Going through all the combinations, one can come up with quite a lengthy set of possible values which we can reduce by leaving reference divider to one. When going through the list of divisor combinations for a particular sample rate, there's definitely a few that do not appear in that drop down menu (and this is excluding the ones where the reference divider is set 2 to 4) so I'm assuming the list that the Vivado IP exposes is considered the "optimal" one?

Also, it's still not clear to me how Vivado decides a "default" reference clock setting when dropping down the IP. For instance, doing some TCL scripting to instantiate a RF Data Converter core for a 2.0 Gsps ADC/DAC tile will always give a default reference clock of 250 MHz and 400 MHz for both ADC and DAC. 

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Contributor
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Registered: ‎10-23-2018

Re: RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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Hi @klumsde,

I'd like to piggy back on this as I am having the same questions. Why are some frequencies and divider ratios left out of the Vivado IP configurator for a certain sample frequency?  Does this mean that we should not use these combinations? For instance, to get to a sampling frequency of 1.33 Gsps, one could use a 250 MHz reference clock with FBdiv = 16 and OUTdiv(M) = 3, but this is not given in the IP configurator.  Is there a general rule of thumb or any insight you can give to selecting these values? Should FBdiv be as high as possible for the best performance?

Also, as asked earlier, does the configuration in the Vivado IP block and the software need to match? Meaning, if I use a different reference clock value & divider ratios in the IP configurator, but then re-configure the RF Data Converter in software using the XRFdc_DynamicPLLConfig function call, will this this work to properly configure the ADC PLL to the proper sampling rate as specified in software? 

Thanks in advance and I look forward to your response,

-Jim

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Moderator
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Registered: ‎04-18-2011

Re: RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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Hi Jim 

I need to check if this is intentional or an oversight. 

I need to look closely at what happens in that api. If I remember you pass it sample rate and refclk.. 

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Adventurer
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Registered: ‎11-14-2008

Re: RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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Right, the rftool api takes <RefClkFreq> and <SamplingRate> as args.

Thanks for looking into this!

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Moderator
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Re: RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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I expect the reason here is that FVCO is going to be too low. 

The VCO should be running at between 8.5Ghz and 12.8Ghz...

In your example here i reckon you are only getting 4GHz..

Keith 

 

 

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Moderator
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Re: RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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Also, in the SW driver the XRFdc_DynamicPLLConfig takes in the FS and in reference clock you give it and then calls XRFdc_SetPLLConfig to set up the PLL 

 

In here you will see that it Checks R

Next it sweeps the valid values for FBDiv, multiplies by the REFCLK frequency to get a FVCO that is in spec, once it does that it sweeps the output divider to find a PLL output that best matches your requested FS. 

So the short answer is that it won't allow you to pick an FVCO that is not in the 8.5Ghz and 12.8Ghz range. 

I hope that this clears it up. 

 

Keith 

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Contributor
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Registered: ‎10-23-2018

Re: RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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Awesome, thanks @klumsde!  It definitely clears it up and I appreciate the help.

 

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Adventurer
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Registered: ‎11-14-2008

Re: RFSoC: RF Data Converter (2.0) PLL Reference Clock IP settings question (ZCU111)

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Extremely helpful. Thanks Keith!
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