RFSoC RFDC AXI Stream

[lalitbhambhani]

Hi @pthakare 

I've written a custom wrapper for to meet AXIS protocol as described in PG269. This data stream is sent to the DUC and then eventually transmitted out over a DAC. I have attached 2 screen shots of the AXIS from system ILA. My question is that do I need to provide a continuous stream to RFDC? This should be a standard AXIS protocol.

In the screenshots, you'll notice that I'm bursting 128 IQ sample pairs per TVALID followed by a 86 AXIS clock cycle delay.

Thanks.

[pthakare]

Hi @lalitbhambhani 

It is AXI4 stream interface.

For the continues analog output from the DAC  you should feed the continues stream .

Check RF-ADC input to output timing diagrams for different configurations where you can see continues stream is feed.

[lalitbhambhani]

Thanks @pthakare 

I now have a constant stream of IQ samples going to RFDC but my spectrum still looks same as non-continuous samples. The samples I'm sending is continuous sinusoidal tone. I'm looking into configuration of the IP and have more questions. I am configuring the RFDC using API.

I used XRFdc_GetBlockStatus() and below are the values I get. I can't find any documentation that provides any context to the values I've received for Analog Data Path Status and Digital Data Path Status, and other read backs. What does 16, 8321, and 3 mean?

Tile 1 DAC 3 Block Status =>
Sampling Freq - 0.512000 GHz
AnalogDataPathStatus - 16 
DigitalDataPathStatus - 8321
DataPathClockStatus - 1
IsFIFOFlagsEnabled - 3
IsFIFOFlagsAsserted - 3

I'm using Tile 1, DAC 3. Is that why I'm getting 3 and -1 for I and Q data paths when I call XRFdc_GetConnectedIData() and XRFdc_GetConnectedQData(). Should I not be using DAC 3. I've set the mixer as IQ -> Real.

DAC 3 DigitalDataPath -> Connected I data = 3
DAC 3 DigitalDataPath -> Connected Q data = -1

Thanks.

[pthakare]

Hi @lalitbhambhani 

Decode the values you are getting using "struct XRFdc_BlockStatus " Section in PG269  page 180.

IsFIFOFlagsEnabled - 3
IsFIFOFlagsAsserted - 3

are not valid values . This should either have "0" or "1" (FIFO flags enabled mask; 1 is enabled, otherwise 0.).

Please share your block design and Data converter  IP configuration file (.XCI) one to check the connection and verify the configuration settings. 

Additionally please request access to starter design lounge there are some example designs available to start with 

https://www.xilinx.com/member/zuplus_rfsoc_starter_designs.html#documents

[lalitbhambhani]

I removed all IP configurations from software and used the default hardware settings and I started seeing the signal I was expecting so I believe my wiring is correct. I will go through each API step by step to verify if I have a wrong setting.

[lalitbhambhani]

Hi  @pthakare 

I have been working on the ADC side and configuring the IP for single real input and IQ output. In PG269 page 142, says I need to enable two subsequent ADCs if I want to convert a real signal to IQ. I'm have enabled Tile 224 ADC 0 and 1. Do I need to tie same analog input to both Vin ports of the ADC or can I leave second port open?

For each ADC I get two outputs, M00 and M01 for ADC0 and M02 and M03 for ADC1. I see I samples on M00 and M02, and Q samples on M01 and M03. If the samples duplicated on outputs then what is the purpose of enabling second ADC?

Thanks.

[pthakare · Accepted solution]

Hi @lalitbhambhani 

For Real Input to I/Q Output  configuration for ADC , you dont need to enable second ADC

Digital Output Data: Sets the data type of the selected converter within the selected tile. The parameter is only configurable when the converter is enabled. Valid values are Real and I/Q.
When converter 0 is set to I/Q, converter 1 must also be enabled and when converter 2 is set to I/Q, converter 3 must also be enabled; otherwise the configuration is invalid.

It means that when converter is set to  I/Q to I/Q configuration where RFADCs are paired

I hope this clarfies.