UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Participant dlee32
Participant
1,363 Views
Registered: ‎05-30-2018

RFSoC XM500 Balun board - differential connection issues

Hello, I am trying to deploy a design I’ve created for the ZCU111 that targets all 8x8 ADC/DAC tiles. I’ve successfully tested a 2x2 system with the XM500 balun board by sending an NCO tone over to the DAC and into the ADC. There’s a few questions/issues that I would like to address.

Main problem

I’m not able to see an NCO tone (ranging from 0 to 250 MHz) on the differential outputs DAC/ADCs such as J32-J37,J39 and J40 on the XM500 Balun board. Non-differential SMA connections seem fine (J5,6,7,8). For differential connections, I am simply just connecting P to P and N to N for the channels of interest. The differential connections I’ve tried are the following channels below:

image.png

image.png

 

Setup Description

My method for verifying if the ADC/DAC channels are correctly hooked up is by examining the one appears on the other side from DAC->ADC. In the simplified 2x2 testing this works fine. More specifically, this test was constrained to the non-differential SMA pin-outs of the XM500 board.  This is represented by “block 229” on the Balun board : DAC04 (J7), DAC05(J8), DAC06(J5) and DAC07(J6) which are represented by DAC Tile 1 Slice 0,1,2 and 3.

The ADC channel tested against a non-differential SMA pin-out “ADC_00” or “J4” on the Balun which represents Tile0 Ch0. Testing an NCO (range from 0 to 250 MHz) J5 to J8 on the DAC worked fine. There was attenuation observed on J7/J8 but that was due to the Mini-circuit RF low-pass filter component, so this behavior is expected.

 

 

PL Settings

I am using custom non-TRD design. All ADC/DAC tiles are set to match the same settings

  • Sample-rate : 2.0 GSps for ADC/DAC. Mixer disabled
  • PLL enabled
  • Decim/interp: 4
  • 4 samples per clock cycle
  • Nyquist Zone 1
  • Reference clock of 250 MHz – I later configure this in software after a power-up

Because the reference clock requires a 250 MHz and 2 GSPs setting, I use the RFTool to configure this using the “DynamicPLL” setting.

DynamicPLLConfig 0 0 1 250.00 2000

DynamicPLLConfig 1 4 1 250.00 2000

 Side question: it seems that there are only two PLLs I can adjust which the ones are above (ADC tile 0 and DAC tile 4). Trying to adjust the tile argument for DynamicPLLConfig results in errors. I’m not sure why this is.

 

Below is the IP core settings for the device taken from the TCL file of my project.

  set usp_rf_data_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.0 usp_rf_data_converter_0 ]
  set_property -dict [ list \
   CONFIG.ADC0_Enable {1} \
   CONFIG.ADC0_Fabric_Freq {125.000} \
   CONFIG.ADC0_Outclk_Freq {125.000} \
   CONFIG.ADC0_Outdiv {6} \
   CONFIG.ADC0_PLL_Enable {true} \
   CONFIG.ADC0_Refclk_Freq {250.000} \
   CONFIG.ADC1_Enable {1} \
   CONFIG.ADC1_Fabric_Freq {125.000} \
   CONFIG.ADC1_Outclk_Freq {125.000} \
   CONFIG.ADC1_Outdiv {6} \
   CONFIG.ADC1_PLL_Enable {true} \
   CONFIG.ADC1_Refclk_Freq {250.000} \
   CONFIG.ADC2_Enable {1} \
   CONFIG.ADC2_Fabric_Freq {125.000} \
   CONFIG.ADC2_Outclk_Freq {125.000} \
   CONFIG.ADC2_Outdiv {6} \
   CONFIG.ADC2_PLL_Enable {true} \
   CONFIG.ADC2_Refclk_Freq {250.000} \
   CONFIG.ADC3_Enable {1} \
   CONFIG.ADC3_Fabric_Freq {125.000} \
   CONFIG.ADC3_Outclk_Freq {125.000} \
   CONFIG.ADC3_Outdiv {6} \
   CONFIG.ADC3_PLL_Enable {true} \
   CONFIG.ADC3_Refclk_Freq {250.000} \
   CONFIG.ADC_Data_Width00 {4} \
   CONFIG.ADC_Data_Width01 {4} \
   CONFIG.ADC_Data_Width02 {4} \
   CONFIG.ADC_Data_Width03 {4} \
   CONFIG.ADC_Data_Width10 {4} \
   CONFIG.ADC_Data_Width11 {4} \
   CONFIG.ADC_Data_Width12 {4} \
   CONFIG.ADC_Data_Width13 {4} \
   CONFIG.ADC_Data_Width20 {4} \
   CONFIG.ADC_Data_Width21 {4} \
   CONFIG.ADC_Data_Width22 {4} \
   CONFIG.ADC_Data_Width23 {4} \
   CONFIG.ADC_Data_Width30 {4} \
   CONFIG.ADC_Data_Width31 {4} \
   CONFIG.ADC_Data_Width32 {4} \
   CONFIG.ADC_Data_Width33 {4} \
   CONFIG.ADC_Decimation_Mode00 {3} \
   CONFIG.ADC_Decimation_Mode01 {3} \
   CONFIG.ADC_Decimation_Mode02 {3} \
   CONFIG.ADC_Decimation_Mode03 {3} \
   CONFIG.ADC_Decimation_Mode10 {3} \
   CONFIG.ADC_Decimation_Mode11 {3} \
   CONFIG.ADC_Decimation_Mode12 {3} \
   CONFIG.ADC_Decimation_Mode13 {3} \
   CONFIG.ADC_Decimation_Mode20 {3} \
   CONFIG.ADC_Decimation_Mode21 {3} \
   CONFIG.ADC_Decimation_Mode22 {3} \
   CONFIG.ADC_Decimation_Mode23 {3} \
   CONFIG.ADC_Decimation_Mode30 {3} \
   CONFIG.ADC_Decimation_Mode31 {3} \
   CONFIG.ADC_Decimation_Mode32 {3} \
   CONFIG.ADC_Decimation_Mode33 {3} \
   CONFIG.ADC_Slice00_Enable {true} \
   CONFIG.ADC_Slice01_Enable {true} \
   CONFIG.ADC_Slice02_Enable {true} \
   CONFIG.ADC_Slice03_Enable {true} \
   CONFIG.ADC_Slice10_Enable {true} \
   CONFIG.ADC_Slice11_Enable {true} \
   CONFIG.ADC_Slice12_Enable {true} \
   CONFIG.ADC_Slice13_Enable {true} \
   CONFIG.ADC_Slice20_Enable {true} \
   CONFIG.ADC_Slice21_Enable {true} \
   CONFIG.ADC_Slice22_Enable {true} \
   CONFIG.ADC_Slice23_Enable {true} \
   CONFIG.ADC_Slice30_Enable {true} \
   CONFIG.ADC_Slice31_Enable {true} \
   CONFIG.ADC_Slice32_Enable {true} \
   CONFIG.ADC_Slice33_Enable {true} \
   CONFIG.DAC0_Enable {1} \
   CONFIG.DAC0_Fabric_Freq {125.000} \
   CONFIG.DAC0_Outclk_Freq {125.000} \
   CONFIG.DAC0_Outdiv {6} \
   CONFIG.DAC0_PLL_Enable {true} \
   CONFIG.DAC0_Refclk_Freq {250.000} \
   CONFIG.DAC0_Sampling_Rate {2.0} \
   CONFIG.DAC1_Enable {1} \
   CONFIG.DAC1_Fabric_Freq {125.000} \
   CONFIG.DAC1_Outclk_Freq {125.000} \
   CONFIG.DAC1_Outdiv {6} \
   CONFIG.DAC1_PLL_Enable {true} \
   CONFIG.DAC1_Refclk_Freq {250.000} \
   CONFIG.DAC1_Sampling_Rate {2.0} \
   CONFIG.DAC_Data_Width00 {4} \
   CONFIG.DAC_Data_Width01 {4} \
   CONFIG.DAC_Data_Width02 {4} \
   CONFIG.DAC_Data_Width03 {4} \
   CONFIG.DAC_Data_Width10 {4} \
   CONFIG.DAC_Data_Width11 {4} \
   CONFIG.DAC_Data_Width12 {4} \
   CONFIG.DAC_Data_Width13 {4} \
   CONFIG.DAC_Interpolation_Mode00 {3} \
   CONFIG.DAC_Interpolation_Mode01 {3} \
   CONFIG.DAC_Interpolation_Mode02 {3} \
   CONFIG.DAC_Interpolation_Mode03 {3} \
   CONFIG.DAC_Interpolation_Mode10 {3} \
   CONFIG.DAC_Interpolation_Mode11 {3} \
   CONFIG.DAC_Interpolation_Mode12 {3} \
   CONFIG.DAC_Interpolation_Mode13 {3} \
   CONFIG.DAC_Slice00_Enable {true} \
   CONFIG.DAC_Slice01_Enable {true} \
   CONFIG.DAC_Slice02_Enable {true} \
   CONFIG.DAC_Slice03_Enable {true} \
   CONFIG.DAC_Slice10_Enable {true} \
   CONFIG.DAC_Slice11_Enable {true} \
   CONFIG.DAC_Slice12_Enable {true} \
   CONFIG.DAC_Slice13_Enable {true} \
 ] $usp_rf_data_converter_0

 

Diagnostics Info

 

I believe the correct tiles should be operating correctly. Here is the output of a register map:

Common Status register (0x0224)
DAC Tile1: 0x0000FE4F
DAC Tile2: 0x0000FE4F
DAC Tile3: 0x00000000
DAC Tile4: 0x00000000
ADC Tile1: 0x0000EAEF
ADC Tile2: 0x0000486F
ADC Tile3: 0x0000406F
ADC Tile4: 0x0000E06F

Current State register (0x000C)
DAC Tile1: 0x0000000F
DAC Tile2: 0x0000000F
DAC Tile3: 0x00000000
DAC Tile4: 0x00000000
ADC Tile1: 0x0000000F
ADC Tile2: 0x0000000F
ADC Tile3: 0x0000000F
ADC Tile4: 0x0000000F

0 Kudos
1 Reply
Highlighted
Adventurer
Adventurer
1,319 Views
Registered: ‎11-14-2008

Re: RFSoC XM500 Balun board - differential connection issues

I think you're seeing a problem with DC bias when connecting the coax cables directly in loopback.

This works for the XM500 paths with baluns because they have AC coupling caps, but the differential paths are direct so you'll need a DC blocker in line..

PG269 (page 65) mentions this for "DAC Analog Outputs"

Also mentioned in UG1309 in the Loopback Test Steps section.

 

Tags (2)