09-08-2020 07:41 AM
I anticipate sourcing an ADC sampling clock of 2GHz (to all 16 ADC channels of the ZU49DR on the Xilinx ZCU216 evaluation board) and would like to synchronize the internal digital processing to the sampling clock.
Referencing the RF-ADC clock structure in "Figure 74: RF-ADC Clock Structure in a Tile" of PG269 (and shown in attached image), the digital processing blocks mentioned above will reside in all three clock domains on the bottom of the illustration. Assuming “Clock” in the illustration is the ADC sampling clock, is “SYSREF” required (assuming the sampling clock can be divided down and driven out into the digital processing domain)? If the 2GHz sampling clock can’t be divided down and distributed to the processing fabric, does “SYSREF” get distributed to the lower clock domains (is synchronized to “Clock” and can be used to clock the digital processing blocks)?
09-16-2020 06:52 PM
Sorry for the late reply.
Yes, the sampling reference clock can be divided down to a lower frequency and propagating out. In most case, it is used as the clocking for the digital data interface. Sysref clock is used for synchronization between different tiles. The frequency of this clock is alway below 10Mhz and it usually only be used for synchronization. For detail information, you can refer to PG269 Pg120 "Multi-tile synchronization" section.
Hope my answer can still help.