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Visitor
Visitor
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Registered: ‎07-01-2020

RFSoC analog bandpass filter requirements

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Hi, wondering what the general recommendations are for an analog bandpass filter that would support 1.25GHz of IBW with the RFSoC. Frequency plan is to have the RF input to the RFSoC from 0.5GHz-1.75GHz in the first Nyquist zone.  Normally in a typical receiver application I would have a pretty high performance analog lowpass and highpass combination to make a bandpass filter, centered at 1.125GHz with 1.25GHz of bandwidth, this filter would have ~20dB of rejection/100MHz as an example. I understand the analog filter requirements are relaxed with the higher sampling rate ADC and you are relying more on the DDC filter in the FPGA but is there a good general guideline for the analog filters with this new architecture?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-20-2018

Usually the analog bandpass filter requirements is based on the DUT SFDR SPEC. You can check the DS926 about the RFSoC HD2 HD3 Interleave spur SPEC. Then  you can check the requirement for the design according the frequency planner on the target frequency points.

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Xilinx Employee
Xilinx Employee
173 Views
Registered: ‎08-20-2018

Usually the analog bandpass filter requirements is based on the DUT SFDR SPEC. You can check the DS926 about the RFSoC HD2 HD3 Interleave spur SPEC. Then  you can check the requirement for the design according the frequency planner on the target frequency points.

View solution in original post